Questions about ADC_CLK of sample code ADC_MPC5744P

[eddiepeng]

Hi everyone,

I'm tracing code of ADC_MPC5744P.

But i'm confusing about ADC_CLK.

At line 81,set ADL_CLK to  32MHz from divide PLL0_PHI by 5 (160 / 5 = 32) 

But in ADC1_Calibration, 

At line 30 , what is the comment mean bus clock? Is it at ADCD?

To my understanding ,bus clock maybe is the peripheral clocka(PBRIDFE0_CLK).

But  it set to 40MHz in this sample.

So i really don't know the comment  tell about bus clock(80MHz)...

If someone know about this, plz give me a hand ...

I'll appreciate for that.

Thanks.

[PetrS]

Hi,

that comment comes from different example, most probably the MPC5748G, which has FS80 clock.

As the ADC_CLK is driven from the AUX clock selector 0

the correct comment for that code should be

MC_CGM.AC0_SC.B.SELCTL = 0b10; //Select PLL0_PHI as source of ADC analog clock

MC_CGM.AC0_DC2.R = 0x80040000; //Enable ADC_CLK and divide PLL0_PHI source by 5 (i.e. 4+1)

ADC_1.MCR.B.ADCLKSEL = 0; /* ADC clock = (PLL0_PHI / 5) / 2  */

BR, Petr

[eddiepeng]

Hi Peter,

Thanks for your answer.

So i stucked in the wrong comment....

The clock of ADC_CLK that you say is the same as what i think.

I'm appreciate that.

Thanks a lot.

Eddie