Power Architecture DMA and CPUs How to Access Bus

[1468682453]

Hello, please ask how the PWOER architecture MCU (MPQ5744P) DMA and CPUs are accessing the bus, is the CPU and DMA alternately using the memory bus, or the CPU priority, if you know that document, please tell me or send it Link to me, thank you very much.

[davidtosenovjan]

You can see following thread, where I have been explained to someone principle of XBAR arbitration:

https://community.nxp.com/t5/MPC5xxx/What-is-the-advantage-of-Crossbar-Switch/m-p/682190

Then I would point out device's RM, Chapter 17 Crossbar Switch (XBAR)

Hope it helps