In the following code you will find the EBI Configuration in my application for MPC5777C and D_CS0 is configured to access external SRAM memory and D_CS1 is configured to access external RTRAM memory
void ExternalMemConfiguration()
{
vuint32_t count = 0;
/* Change EBI Physical Base Address to 0x2000_0000 */
External_SRAM_MMU_init();
//SIU.ECCR.R = 0x00001000;
// SIU.ECCR.R = 0x00000181;
/* CS0 PCR 256 */
SIU.PCR[256].R = 0x044C;
/* CS1 PCR 301 */
SIU.PCR[301].R = 0x044C;
/* CS2 PCR 257 */
SIU.PCR[257].R = 0x044C;
/* CS3 PCR 258 */
SIU.PCR[258].R = 0x044C;
/* D_RD_WR PCR 294 */
SIU.PCR[294].R = 0x044C;
/* D_WE0 - D_WE1 PCR 295-296 */
SIU.PCR[295].R = 0x044C;
SIU.PCR[296].R = 0x044C;
/* D_OE PCR 297 */
SIU.PCR[297].R = 0x044C;
/* D_TS PCR 298 */
SIU.PCR[298].R = 0x044C;
/* D_ALE PCR 299 */
SIU.PCR[299].R = 0x044C;
/* D_TA PCR 300 */
SIU.PCR[300].R = 0x044C;
/* D_BDIP PCR 302 */
SIU.PCR[302].R = 0x044C;
/* D_WE2 - D_WE3 PCR 303 - 304 */
SIU.PCR[303].R = 0x044C;
//SIU.PCR[304].R = 0x044C;
/* D_ADD9 - D_ADD11 PCR 305 - 307 */
for (count = 305; count <= 307; count++)
{
SIU.PCR[count].R = 0x044C;
};
/* D_ADD12 - D_ADD15 PCR 259 - 262 */
for (count = 259; count <= 262; count++)
{
SIU.PCR[count].R = 0x044C;
};
/* D_ADD16 - D_ADD30 PCR 263 - 277 */
for (count = 263; count <= 277; count++)
{
SIU.PCR[count].R = 0x044C;
};
/* D_DAT0 - D_DAT15 PCR 278 - 293 */
for (count = 278; count <= 293; count++)
{
SIU.PCR[count].R = 0x044C;
};
//EBI.BMCR.B.BME = 0x0; //Bus Monitor Disabled
/*Base Address: 0x20000803, 16-bit, NoN Mux'd bus */
EBI.CAL[0].BR.R = 0x20001921; //LWRN =1, PS=1,BI=1,V=1,SBL=0,WEBS=1
/* Address Mask: 16MB, Zero Wait States - Flow-Through Sync SRAM */
EBI.CAL[0].OR.R = 0xFF000000;
/* Base Address: 0x20400803, 16-bit, NoN Mux'd bus */
EBI.CAL[1].BR.R = 0x21000807;
/* Address Mask: 16MB, 2 Wait States - */
EBI.CAL[1].OR.R = 0xFF0000F0;
/* Base Address: 0x20800803, 16-bit, NoN Mux'd bus */
EBI.CAL[2].BR.R = 0x22001807;//0x20410803
/* Address Mask: 16MB, 2 Wait States - */
EBI.CAL[2].OR.R = 0xFF0000F0; //8 wait states*/
/* /* Base Address: 0x20C00803, 16-bit, NoN Mux'd bus */
EBI.CAL[3].BR.R = 0x23001801;
/* Address Mask: 16MB, 2 Wait States - */
EBI.CAL[3].OR.R = 0xFE0000F0;
/* MCR - 16-bit mode */
EBI.MCR.R = 0x00000001;
}
void External_SRAM_MMU_init(void)
{
//asm("nofralloc");
asm("lis r3, 0x1002"); /* Select TLB entry #, define R/W replacment control */
asm("mtMAS0 r3"); /* Load MAS0 with 0x1002 0000 for TLB entry #2 */
asm("tlbre"); /* Get TLB entry # information */
asm("mfspr r3, MAS3");
asm("oris r3, r3, 0x2000"); /* EBI Physical Base Addr changed to 0x2000_0000 */
asm("ori r3, r3, 0x0000");
asm("mtMAS3 r3");
asm("msync"); /* make sure we finished all memory accesses */
asm("tlbwe"); /* Write entry defined in MAS0 (entry 1 here) to MMU TLB */
asm("isync"); /* Wait for tlbwe to complete, then flush instruction buffer */
asm("blr");
}
external SRAM memory is accessed through address location - 0x206C2000
external RTRAM memory is accessed through address location - 0x21004000
After accessing (i.e. write operation) external SRAM memory location if external RTRAM memory is accessed (i.e. write operation) it is observed that expected data is not found in the above RTRAM memory address location, please clarify how MPC5777C controller will differentiate these memory locations for different devices as only address lines D_ADD09-D_ADD30 is connected to memory devices
