MPC5775K how to sleep individual cores?

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MPC5775K how to sleep individual cores?

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joeshidle
Contributor II

On the MPC5775K is it possible to place individual cores into low-power states while the other core(s) are still running?

 

For example, if I have the Z4_1 core working on Task A while the Z7_2 is working on Task B.  If the Z4_1 needs to delay for some time (wait on external interrupt, wait on Z7_2 to finish part of Task B, etc.) I'd like to place Z4_1 into a low-power mode instead of spinning in a while() delay loop while waiting.

 

It seems like the MC_ME registers (e.g. MC_ME.HALT0_MC) and WKPU registers are whole-chip.  But I didn't know if the intent was to use the MC_ME.CCTL1/2/3 registers to regulate individual core behavior in normal run modes.

So first, can individual cores be dynamically halted / restarted for in-run power savings?

And if so, how would that be achieved?

Thanks in advance,

Joe Shidle

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joeshidle
Contributor II

I may have answered my own question.  I am not seeing the asm("wait") exit from a PIT timer interrupt.

How would NXP recommend implementing a "sleep for N milliseconds" type of behavior for circumstances when one of the cores is idle (while one or both of the other cores are still working)?

Thanks in advance,

Joe Shidle

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martin_kovar
NXP Employee
NXP Employee

Hello Joe,

unfortunately, Mode Entry module is common for all three cores, so it is not possible to switch individual cores to different modes.

But as you wrote, there are CCTL registers which allows you to enable/disable individual cores in different modes. So you can disable required core/cores in some mode and switch microcontroller between this modes.

You can also use WAIT instruction, but it does not switch core to low power mode. The wait instruction stops synchronous processor activity including the fetching of instructions until an asynchronous interrupt, a debug post-completion (ICMP) interrupt occurs, or the event specified by the WC operand occurs. A processor typically uses this to reduce power consumption.

If you have any other questions, please feel free to write me back.

Regards,

Martin

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joeshidle
Contributor II

Martin;

Thank you for the response.  I assume you are referring to the PPC e200 assembly WAIT instruction (e.g. asm("wait") ). A quick test with one of the cores that is handling serial communication, the serial RX interrupt does seem to cause it to exit from the 'wait'. 

I would like to use one of the PITs as a timer to cause a wake after timer expiration.  So I'd like to clarify the use of "asynchronous" vs. "synchronous" interrupts.  I have generally considered HW timers to be asynchronous as they generate IRQs, as opposed to the traditional synchronous interrupts (exceptions like divide-by-zero, etc.).  But some architectures consider timers, since they are CPU-clocked, to be synchronous.  Could I use a PIT or eTimer to wake a core from a "wait" instruction?

Additionally, do you know approximately how much power savings is achieved by a core going into a WAIT?  I'm not looking for hard numbers (and certainly won't hold you to them!), a percentage is fine.

Thanks again for your help,
Joe Shidle

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martin_kovar
NXP Employee
NXP Employee

Hello Joe,

sorry for delay. Wait instruction has one problem. If you use wait for "stop" the core, every incoming interrupt wake up the core from "stop" state. So you can definitely use PIT or eTImer to wake the core.

But from my point of view, there is better solution. Use Mode Entry module and enable/disable cores in each RUN mode as required. There are four RUN modes, so you can create four configurations. Then you can use configure PIT timer and use interrupt to change RUN mode. After you execute the required code, you switch microcontroller to another RUN mode. This function allows you to enable/disable cores as required. Do not hesitate to use Mode Entry module, because these RUN modes are created for this purpose.

About power consumption while wait is active, I have not measured it, so my answer would have been only random guess.

Regards,

Martin

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