MPC5748G - parameters of flash HSM data block 0 and 1

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MPC5748G - parameters of flash HSM data block 0 and 1

Contributor I

Can you please describe parameters MPC5748G flash memory - read and write speed, optimum size for read and write, especially HSM data block?

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NXP TechSupport
NXP TechSupport



The HSM flash blocks are the same as other flash blocks, so specification from section “6.3 Memory interfaces” is valid:

You can find timing specification for program and erase operations in this section.

There’s a mini-cache in the flash memory controller. If data are already buffered, it allows zero wait state response on buffer hit. If data are not buffered, the timing for read operation is given by wait states – see the section “6.3.6 Flash read wait state and address pipeline control settings” for more details.


Regarding optimum size – the flash can be programmed by double word (64bit), page (256bit) or quad page (1024bit). If you check the timing in Table 30 in datasheet, the best result will be achieved when quad page programming is used.

You can read byte, halfword or word (32bit), so the most effective is reading of words, of course. The width of data bus between flash array and flash controller is 256bits, so any read access will cause (on buffer miss when data are not available in mini-cache) that whole 256bit line is loaded from flash array.




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