Hi,
The header file MPC5746C.h v4.0.0 is missing the Registers LTMR64H and LTMR64L.
I believe this is how it's supposed like.
struct PIT_tag {
PIT_MCR_tag MCR; /* PIT Module Control Register */
uint8_t PIT_reserved0[232];
PIT_LTMR64H_tag LTMR64H /*Upper Lifetime Timer Register */
PIT_LTMR64L_tag LTMR64L /*Lower Lifetime Timer Register */
PIT_RTI_LDVAL_tag RTI_LDVAL; /* Timer Load Value Register */
PIT_RTI_CVAL_tag RTI_CVAL; /* Current Timer Value Register */
PIT_RTI_TCTRL_tag RTI_TCTRL; /* Timer Control Register */
PIT_RTI_TFLG_tag RTI_TFLG; /* Timer Flag Register */
PIT_TIMER_tag TIMER[16];
typedef union PIT_LTMR64H_union_tag { /* Upper Lifetime Timer Register */
vuint32_t R;
struct {
vuint32_t LTMR64H:32;
} B;
} PIT_LTMR64H_tag;
typedef union PIT_LTMR64L_union_tag { /* Lower Lifetime Timer Register */
vuint32_t R;
struct {
vuint32_t LTMR64L:32;
} B;
} PIT_LTMR64L_tag;
#define PIT_LTMR64H PIT.LTMR64H.R
#define PIT_LTMR64L PIT.LTMR64L.R
Thank you.
PIT module listing follows.
/* ============================================================================
=============================== Module: PIT ================================
============================================================================ */
typedef union PIT_MCR_union_tag { /* PIT Module Control Register */
vuint32_t R;
struct {
vuint32_t _unused_3:29;
vuint32_t MDIS_RTI:1; /* Module Disable - RTI section */
vuint32_t MDIS:1; /* Module Disable - (PIT section) */
vuint32_t FRZ:1; /* Freeze */
} B;
} PIT_MCR_tag;
typedef union PIT_RTI_LDVAL_union_tag { /* Timer Load Value Register */
vuint32_t R;
struct {
vuint32_t TSV:32; /* Timer Start Value */
} B;
} PIT_RTI_LDVAL_tag;
typedef union PIT_RTI_CVAL_union_tag { /* Current Timer Value Register */
vuint32_t R;
struct {
vuint32_t TVL:32; /* Current Timer Value */
} B;
} PIT_RTI_CVAL_tag;
typedef union PIT_RTI_TCTRL_union_tag { /* Timer Control Register */
vuint32_t R;
struct {
vuint32_t _unused_2:30;
vuint32_t TIE:1; /* Timer Interrupt Enable */
vuint32_t TEN:1; /* Timer Enable Bit */
} B;
} PIT_RTI_TCTRL_tag;
typedef union PIT_RTI_TFLG_union_tag { /* Timer Flag Register */
vuint32_t R;
struct {
vuint32_t _unused_1:31;
vuint32_t TIF:1; /* Timer Interrupt Flag. */
} B;
} PIT_RTI_TFLG_tag;
typedef union PIT_TIMER_LDVAL_union_tag { /* Timer Load Value Register */
vuint32_t R;
struct {
vuint32_t TSV:32; /* Timer Start Value */
} B;
} PIT_TIMER_LDVAL_tag;
typedef union PIT_TIMER_CVAL_union_tag { /* Current Timer Value Register */
vuint32_t R;
struct {
vuint32_t TVL:32; /* Current Timer Value */
} B;
} PIT_TIMER_CVAL_tag;
typedef union PIT_TIMER_TCTRL_union_tag { /* Timer Control Register */
vuint32_t R;
struct {
vuint32_t _unused_3:29;
vuint32_t CHN:1; /* Chain Mode */
vuint32_t TIE:1; /* Timer Interrupt Enable */
vuint32_t TEN:1; /* Timer Enable */
} B;
} PIT_TIMER_TCTRL_tag;
typedef union PIT_TIMER_TFLG_union_tag { /* Timer Flag Register */
vuint32_t R;
struct {
vuint32_t _unused_1:31;
vuint32_t TIF:1; /* Timer Interrupt Flag */
} B;
} PIT_TIMER_TFLG_tag;
typedef struct PIT_TIMER_struct_tag {
PIT_TIMER_LDVAL_tag LDVAL; /* Timer Load Value Register */
PIT_TIMER_CVAL_tag CVAL; /* Current Timer Value Register */
PIT_TIMER_TCTRL_tag TCTRL; /* Timer Control Register */
PIT_TIMER_TFLG_tag TFLG; /* Timer Flag Register */
} PIT_TIMER_tag;
struct PIT_tag {
PIT_MCR_tag MCR; /* PIT Module Control Register */
uint8_t PIT_reserved0[236];
PIT_RTI_LDVAL_tag RTI_LDVAL; /* Timer Load Value Register */
PIT_RTI_CVAL_tag RTI_CVAL; /* Current Timer Value Register */
PIT_RTI_TCTRL_tag RTI_TCTRL; /* Timer Control Register */
PIT_RTI_TFLG_tag RTI_TFLG; /* Timer Flag Register */
PIT_TIMER_tag TIMER[16];
};
