MPC5642A EMIOS Input Capture Error

[tgc-yilmaz]

Hello,

I am using mpc5642a. I aim to read the high time and frequency of the PWM input signal.
There is a 1ms cycle scheduler, but the frequency of the signals I aim to read is around 20-500Hz.
I worked on two different designs for reading PWM input signals.

Design 1: I read the values from the CADR and CBDR register values in each cycle, even though I could not catch the high edge due to the scheduler's minimum cycle time and the targeted high time to read.

// Channel Control Register
/* Freeze Enable: Normal operation */
/* Output Disable: The output pin operates normally */
/* Output Disable Select: Output disable input 0 */
/* Prescaler: Divide ratio 1 */
/* Prescaler Enable: Enable */
/* DMA Memory Access: Assigned to Interrupt */
/* Input Filter: Not Applicable */
/* Filter clock select: Prescaler clock */
/* Flag Enable: IRQ/DMA not generated */
/* Force Match A: Disabled */
/* Force Match B: Disabled */
/* Bus Select: Internal Counter */
/* Edge Selection Bit: Not Applicable */
/* Edge Polarity: Set on Match A */
/* MODE[0-6]: Input Pulse Width Measurement */
EMIOS.CH[1].CCR.R = 0x02000684;

// Function Implementation
void inputCapture()
{
   uint32_t ChannelAData = 0;
   uint32_t ChannelBData = 0;
   uint32_t PulseWidthValue = 0;
   uint32_t PeriodValue = 0;

   // Measure pulse width of signal
   // Wait for flag to be set
   if EMIOS.CH[1].CSR.B.FLAG == 1)
   {
      // Clear FLAG bit
      EMIOS.CH[1].CSR.B.FLAG = 1;
   }

   // Read data from register A and register B
   ChannelAData = EMIOS.CH[1].CADR.R;

   ChannelBData = EMIOS.CH[1].CBDR.R;

   // Calculate pulse width value
   // Normal Case
   if ((EMIOS.CH[1].CSR.B.OVFL != 1) || (ChannelBData < ChannelAData))
   {
      PulseWidthValue = (ChannelAData - ChannelBData);
   }
   else
   {
      PulseWidthValue = (0xFFFFFFFFu - ChannelBData + ChannelAData);

      // Clear Overflow flag
      EMIOS.CH[1].CSR.B.OVFL = 1;
   }
}

Design 2: I read input signals over EDMA.

// Channel Control Register
/* Freeze Enable: Normal operation */
/* Output Disable: The output pin operates normally */
/* Output Disable Select: Output disable input 0 */
/* Prescaler: Divide ratio 1 */
/* Prescaler Enable: Enable */
/* DMA Memory Access: Assigned to DMA request */
/* Input Filter: Not Applicable */
/* Filter clock select: Prescaler clock */
/* Flag Enable: Enable (Flag generates an IRQ/DMA request */
/* Force Match A: Disabled */
/* Force Match B: Disabled */
/* Bus Select: Internal Counter */
/* Edge Selection Bit: Not Applicable */
/* Edge Polarity: Set on Match A */
/* MODE[0-6]: Input Pulse Width Measurement */
EMIOS.CH[1].CCR.R = 0x03020684;

struct EDMA_TCD_STD_tag eMIOSCH1Descriptor =
{
   /* 00 */ /* Load address of source data */
   (vuint32_t) &EMIOS.CH[1].CADR.R, /* SADDR - 32 bit */
   /* 04 */
   0, /* SMOD - 05 bit */
   3, /* SSIZE - 03 bit */
   0, /* DMOD - 05 bit */
   3, /* DSIZE - 03 bit */
   /* 06 */
   0, /* SOFF - 16 bit */
   /* 08 */
   8, /* NBYTES - 32 bit */
   /* 12 */
   0, /* SLAST - 32 bit */
   /* 16 */
   (vuint32) &EMIOSDataRegValues.CADRRegValue, /* DADDR - 32 bit */
   /* 20 */
   0, /* CITERE_LINK - 01 bit */
   (vuint16) 1, /* CITER - 15 bit */
   /* 22 */
   0, /* DOFF - 16 bit */
   /* 24 */
   0, /* DLAST - 32 bit */
   /* 28 */
   0, /* BITERE_LINK - 01 bit */
   (vuint16) 1, /* BITER - 15 bit */
   /* 30 */
   0, /* BWC - 02 bit */
   0, /* MAJORLINKCH - 06 bit */
   0, /* DONE - 01 bit */
   0, /* ACTIVE - 01 bit */
   0, /* MAJORE_LINK - 01 bit */
   0, /* E_SG - 01 bit */
   0, /* D_REQ - 01 bit */
   0, /* INT_HALF - 01 bit */
   0, /* INT_MAJ - 01 bit */
   0 /* START - 01 bit */
};

// Function Implementation
void inputCapture()
{
   uint32_t pulseWidthValue = 0;

   // Measure pulse width of signal
   // Normal Case
   if (EMIOSDataRegValues.CBDRRegValue < EMIOSDataRegValues.CADRRegValue)
   {
      pulseWidthValue = (EMIOSDataRegValues.CADRRegValue -
      EMIOSDataRegValues.CBDRRegValue);
   }
   else
   {
      pulseWidthValue = (0xFFFFFFFFu - EMIOSDataRegValues.CBDRRegValue +
      EMIOSDataRegValues.CADRRegValue);
   }
}

However, in both designs, it has been observed that there is oscillation in the read values even when the input signal is stable. Could there be an error in the code, can you help with this?

Thanks in advance.

[PetrS]

Hi,

maybe the issue is just due to multiple overflows. Not sure of the eMIOS clock used and its global prescaler, but consider this with respect of measured signal duration.
Moreover eMIOS uses 24bit counter, thus in your overflow calculation do not use max 32bit value, but rather 0xFFFFFF.

BR, Petr