Hi ,
I am learning the MPC5634M Microcontroller Reference Manual.
I have some questions about eSCI/LIN receive.
uint8_t LINFlex1MasterSendHeader(void)
{
uint16_t timeout,j;
uint8_t Ret=LINFLEX_E_OK;
uint32_t temp_data = 0;
FrameHeaData[0] = 0x36;
FrameHeaData[1] = 8;
FrameHeaData[2] =0xCF;
FrameHeaData[3] = 0xFF;
for (j=0; j< sizeof (FrameHeaData); j++)
{ /* Loop for character string */
while (ESCI_B.SR.B.TXRDY == 0)
{
timeout++;
if(timeout>LINFLEX_TIMEOUT_VAL)
{
Ret = LINFLEX_E_NOT_OK;
break;
}
else
{
/**/
}
} /* Wait for LIN transmit ready = 1 */
ESCI_B.SR.R = 0x00004000; /* Clear TXRDY flag */
ESCI_B.LTR.R = FrameHeaData[j]; /* Write byte to LIN Trans Reg. */
}
LINFlex1ReceSigh = 0;
return Ret;
}
The resulting waveform is as follows
MPC5634M Microcontroller Reference Manual.
The first byte written to the SCI_LTR contains the Identifier and Identifier Parity fields. The second byte
written defines the number of data bytes requested from the LIN slave. The third write access defines the
CRC and checksum checking. The TD bit has to be set to 0 to invoke the RX frame generation. The TO
field defines the upper part of the timeout value. The fourth byte written defines the lower part of the
timeout value.
After the fourth byte is written the generation of a LIN RX frame starts. Firstly, a break field is transmitted,
then the synch field and the protected identifier field.
The actual operation is not as expected,So please help to analyze the causes of this problem. Thanks
Hi,
how is the LTR defined? Do you really write a BYTE to address offset 0x10?
If LTR is defined as 32 bit register then use this statement
ESCI_B.LTR.R = FrameHeaData[j] << 24;
BR, Petr
Hi, Petr
Thank you for your answer.Your writing is correct.
Thanks