Is this an e200z6 embedded Floating-Point APU implementation issue?

[mikesfn]

In section 3.6.4.1 "Options for Embedded Floating-Point APU Implementations" of the e200z6 PowerPC core manual, the following option implementation is stated:

Option:  If an operand for a calculation or conversion is denormalized, the implementation may choose to use a same-signed zero value in place of the denormalized operand.

e200z6 Implementation: The e200z6 uses a same-signed zero value in place of the denormalized operand.

However, this appears to not be true.

For example, given the following two single-precision float variables with values as shown:

float a = 1.98e-43; //(0x0000008D)

float b = -125; //(0xC2FA0000)

Any equation or comparison between these two operands (ex. "a + b" or "a > b") results in an SPE Data Exception due to inexact result (FINXS and FINVS bits set in the SPEFSCR). Based on the implementation described in the manual above, I would have expected that the FPU would use the "same-signed zero value" in place of the denormalized value stored in variable 'a' and not throw an exception. Have I misunderstood the manual, or is this actually an issue in the floating-point APU of the e200z6 core?

[mikesfn]

Thanks David. That answers it!. I do indeed have FINVE set so that's the reason for the exception.

I guess I missed this statement:

Thanks,

[davidtosenovjan · Accepted solution]

Hi, SPE allows two options single precision floating point capabilities:

1) May be configured to be fully IEEE compliant, in which case awkward corner cases (NaN’s, Infinities, denormalized values) will be handled by software through the raising of exceptions

2) May be configured to be not fully IEEE compliant, in which case arithmetic will saturate or round to zero and no value-dependent exceptions will be raised

Option number 2 is default, so yes, underflow value is replaced by 0 automatically by default.

Pay attention to SPEFSCR bits below: