We are getting a processor reset because of a double bit error on the flash originating from the ECC checks and would like to disable the checks and rely on the check sum to test the integrity of flash.
The only exception is reporting of ECC events on data flash where ECC event reporting is suppressed, single-bit and multi-bit ECC errors are not reported (either to the core or to MEMU module). On multi-bit ECC event, the corrupted read data is replaced with a fixed, ECC-clean illegal opcode value of 0x1555_1555.
Single-bit ECC events on code flash accesses are automatically corrected and reported to the MEMU (if enabled). On multi-bit ECC event, core responds with bus error (IVOR1 exception) and an error is reported to MEMU module.