Confused by DMA count config in fsl_sai_emda

[mttjcksn]

Hi all, 

In SAI_TransferTxSetConfigEDMA of fsl-sai-edma.c, we have the following lines:

#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
    handle->count = (uint8_t)((uint32_t)FSL_FEATURE_SAI_FIFO_COUNTn(base) - saiConfig->fifo.fifoWatermark)

This means that if a FIFO exists, the number of words in the DMA transfer can only be FIFO_SIZE - WATERMARK.

Can someone please explain why this is set because this seems like an unnecessary and problematic limitation to me. Is it trying to make sure the FIFO is always full?

What about real-time low-latency applications that want to transfer a small number of words each request? And what if (FIFO_SIZE - WATERMARK) is not a multiple of the number of words you need to transfer each request?  Currently the driver asserts an error if this is the case. 

Thanks, Matt

[Gavin_Jia · Accepted solution]

Hi @mttjcksn ,

Thanks for your interest in NXP MIMXRT series!

You are right. This assert makes the transmission executing when the FIFO is full. This design is to balance the transmission efficiency and stability. Therefore, for your actual application scenario, you can modify the size of watermark to fit it.

Best regards,
Gavin