What the IDE will do when i check SWO init by IDE for RT1170

[ConstYu]

I am using mcuxpresso+ rt1176 EVK+ mculink, it can work well now, but i want to make such initialization in app code, so i wonder what the IDE will do when i check SWO init by IDE for RT1170, i get know it's related with ERR050708, IDE has made some workaround already. 

https://community.nxp.com/t5/RT-4-Digit-10xx-11xx-12xx/RT1170-SWO-implementation-with-IAR-and-Segger... 

In addition, i also found mcuxpresso+ rt1176 EVK+ Jlink plus can't work, not sure whether it's the issue of my configuration or mcuxpresso didn't support such feature yet.

PS: i found the log is as below after make SWO configuration in MCUXPresso, i found it said the SWO enabled successfully, my question is how IDE enable SWO, I want to know which registers are needed to configure. 

Received monitor command: SWO DisableTarget 0
SWO disabled successfully.
Received monitor command: SWO GetMaxSpeed 66000000
Maximum supported SWO speed is 6000000 Hz.
Received monitor command: SWO GetSpeedInfo
Base frequency: 48000000Hz, MinDiv: 8
Received monitor command: SWO EnableTarget 66000000 6000000 1 0
SWO enabled successfully.
Read 4 bytes @ address 0xE0001FB4 (Data = 0x00000000)
Read 4 bytes @ address 0xE0001000 (Data = 0x40000001)
Reading 60 bytes @ address 0xE0001020
Downloading 4 bytes @ address 0xE0001020 - Verified OK
Downloading 4 bytes @ address 0xE0001024 - Verified OK
Downloading 4 bytes @ address 0xE0001028 - Verify failed
Downloading 4 bytes @ address 0xE000102C - Verified OK
Downloading 4 bytes @ address 0xE0001030 - Verified OK
Downloading 4 bytes @ address 0xE0001034 - Verified OK
Downloading 4 bytes @ address 0xE0001038 - Verified OK
Downloading 4 bytes @ address 0xE000103C - Verified OK
Downloading 4 bytes @ address 0xE0001040 - Verified OK
Downloading 4 bytes @ address 0xE0001044 - Verified OK
Downloading 4 bytes @ address 0xE0001048 - Verify failed
Downloading 4 bytes @ address 0xE000104C - Verified OK
Downloading 4 bytes @ address 0xE0001050 - Verified OK
Downloading 4 bytes @ address 0xE0001054 - Verified OK
Downloading 4 bytes @ address 0xE0001058 - Verify failed
Reading 60 bytes @ address 0xE0001020
Downloading 4 bytes @ address 0xE0001020 - Verified OK
Downloading 4 bytes @ address 0xE0001024 - Verified OK
Downloading 4 bytes @ address 0xE0001028 - Verified OK
Downloading 4 bytes @ address 0xE000102C - Verified OK
Downloading 4 bytes @ address 0xE0001030 - Verified OK
Downloading 4 bytes @ address 0xE0001034 - Verified OK
Downloading 4 bytes @ address 0xE0001038 - Verified OK
Downloading 4 bytes @ address 0xE000103C - Verified OK
Downloading 4 bytes @ address 0xE0001040 - Verified OK
Downloading 4 bytes @ address 0xE0001044 - Verified OK
Downloading 4 bytes @ address 0xE0001048 - Verified OK
Downloading 4 bytes @ address 0xE000104C - Verified OK
Downloading 4 bytes @ address 0xE0001050 - Verified OK
Downloading 4 bytes @ address 0xE0001054 - Verified OK
Downloading 4 bytes @ address 0xE0001058 - Verified OK
Read 4 bytes @ address 0xE0000E00 (Data = 0x00000001)
Read 4 bytes @ address 0xE0000E80 (Data = 0x0001000D)
Read 4 bytes @ address 0xE0045FB4 (Data = 0x00000001)
Read 4 bytes @ address 0xE0045FF0 (Data = 0x0000000D)
Read 4 bytes @ address 0xE0045FF4 (Data = 0x00000090)
Read 4 bytes @ address 0xE0045FF8 (Data = 0x00000005)
Read 4 bytes @ address 0xE0045FFC (Data = 0x000000B1)
Read 4 bytes @ address 0xE0045FE0 (Data = 0x00000008)
Read 4 bytes @ address 0xE0045FE4 (Data = 0x000000B9)
Read 4 bytes @ address 0xE0045FE8 (Data = 0x0000003B)
Read 4 bytes @ address 0xE0045FEC (Data = 0x00000000)
Read 4 bytes @ address 0xE0045FD0 (Data = 0x00000004)
Read 4 bytes @ address 0xE0045FC8 (Data = 0x00000032)
Read 4 bytes @ address 0xE0045000 (Data = 0x00000303)
Read 4 bytes @ address 0xE0045FB4 (Data = 0x00000001)
Read 4 bytes @ address 0xE0045FB0 (Data = 0x00000000)
Read 4 bytes @ address 0xE0045FB0 (Data = 0x00000000)
Downloading 4 bytes @ address 0xE0045FB0 - Verify failed
Read 4 bytes @ address 0xE0045FB0 (Data = 0x00000000)
Read 4 bytes @ address 0xE0045FB4 (Data = 0x00000001)
Read 4 bytes @ address 0xE0048FB4 (Data = 0x00000001)
Read 4 bytes @ address 0xE0048FB4 (Data = 0x00000001)
Read 4 bytes @ address 0xE0048FB0 (Data = 0x00000000)
Read 4 bytes @ address 0xE0048FB0 (Data = 0x00000000)
Downloading 4 bytes @ address 0xE0048FB0 - Verify failed
Read 4 bytes @ address 0xE0048FB0 (Data = 0x00000000)
Read 4 bytes @ address 0xE0048FB4 (Data = 0x00000001)
Read 4 bytes @ address 0xE0043FB4 (Data = 0x00000000)
Read 4 bytes @ address 0xE0043FF0 (Data = 0x0000000D)
Read 4 bytes @ address 0xE0043FF4 (Data = 0x00000090)
Read 4 bytes @ address 0xE0043FF8 (Data = 0x00000005)
Read 4 bytes @ address 0xE0043FFC (Data = 0x000000B1)
Read 4 bytes @ address 0xE0043FE0 (Data = 0x00000008)
Read 4 bytes @ address 0xE0043FE4 (Data = 0x000000B9)
Read 4 bytes @ address 0xE0043FE8 (Data = 0x0000001B)
Read 4 bytes @ address 0xE0043FEC (Data = 0x00000000)
Read 4 bytes @ address 0xE0043FD0 (Data = 0x00000004)
Read 4 bytes @ address 0xE0043FC8 (Data = 0x00000028)
Read 4 bytes @ address 0xE0043000 (Data = 0x00000300)
Read 4 bytes @ address 0xE0043FB4 (Data = 0x00000000)
Downloading 4 bytes @ address 0xE000EDFC - Verified OK
Read 4 bytes @ address 0xE00480F0 (Data = 0x00000001)
Read 4 bytes @ address 0xE0048010 (Data = 0x00000000)
Downloading 4 bytes @ address 0xE0045000 - Verify failed
Read 4 bytes @ address 0xE0045000 (Data = 0x00000303)
Downloading 4 bytes @ address 0xE0043000 - Verified OK
Read 4 bytes @ address 0xE0043000 (Data = 0x000003FF)
Downloading 4 bytes @ address 0xE00480F0 - Verified OK
Read 4 bytes @ address 0xE00480F0 (Data = 0x00000002)
Downloading 4 bytes @ address 0xE0048010 - Verified OK
Read 4 bytes @ address 0xE0048010 (Data = 0x0000000A)
Downloading 4 bytes @ address 0xE0000E80 - Verified OK
Read 4 bytes @ address 0xE0000E80 (Data = 0x0001000C)
Downloading 4 bytes @ address 0xE0000E80 - Verified OK
Read 4 bytes @ address 0xE0000E80 (Data = 0x0001040A)
Downloading 4 bytes @ address 0xE0000E80 - Verified OK
Read 4 bytes @ address 0xE0000E80 (Data = 0x0001040B)
Downloading 4 bytes @ address 0xE0000E00 - Verified OK

[Aiyps]

Hi,

Please let me know if you were able to solve this issue.

I am facing a similar issue.

If "Force SWO initialization by IDE" checkbox is checked in MCUXpresso IDE,
the SWO signal is output from PB3 of the MIMXRT1170-EVK board.

But if I perform the same operations displayed on the Trace Console using my code, nothing is output on the SWO signal from PB3 of the MIMXRT1170-EVK board.

This is the output from the console:

--------------------------------------------------------------------------------------------------------------------------------------

**---------- Considered CoreSight Components ----------**
DWT 0xE0001000
ITM 0xE0000000
Trace Funnel 0xE0045000
SWO 0xE0048000
Trace Funnel 0xE0043000
ETM 0xE0041000

**---------- Enable use of trace and debug blocks (DWT, ITM, ETM, TPIU) ----------**
*0xE000EDFC = 0x01000000 // DEMCR [Enable trace and debug block]

**---------- Configure SWO ----------**
*0xE0048FB0 = 0xC5ACCE55 // LOCKACCESS [Unlock registers]
*0xE0045FB0 = 0xC5ACCE55 // LOCKACCESS [Unlock registers]
*0xE0045000 = 0x000003FF // CSTF [Program Funnel]
*0xE0043000 = 0x000003FF // CSTF [Program Funnel]
*0xE00480F0 = 0x00000002 // SWO_SPPR [Select NRZ protocol]
*0xE0048010 = 0x00000006 // SWO_CODR [Set prescaler]
*0xE0000E80 = 0x0001000C // ITM_TCR [Disable ITM]
*0xE0000E80 = 0x0001040A // ITM_TCR [Enable DWT->TPIU. Configure timestamp]
*0xE0000E80 = 0x0001040B // ITM_TCR [Enable ITM block]
*0xE0000E00 = 0x00000001 // ITM_TER [Enable stimulus ports]

**---------- Enable ITM_TRACE ----------**
*0xE0000E80 = 0x0001040A // ITM_TCR [Disable ITM]
*0xE0000E80 = 0x0001040B // ITM_TCR [Enable ITM block]
*0xE0000E00 = 0x00000001 // ITM_TER [Enable stimulus ports]
*0xE0000E40 = 0x00000008 // ITM_TPR [Set privileges]

--------------------------------------------------------------------------------------------------------------------------------------

This is my code in which I am performing the same operations:

void SWO_Init(uint32_t cpuCoreFreqHz, uint32_t SWOSpeed)
{
// SWOSpeed in Hz, note that cpuCoreFreqHz is expected to be match the CPU core clock
volatile uint32_t SWOPrescaler = (cpuCoreFreqHz / SWOSpeed) - 1;

// Enable use of trace and debug blocks (DWT, ITM, ETM, TPIU)
*(volatile unsigned int*)0xE000EDFC = 0x01000000; // [DEMCR.TRCENA][Enable trace and debug blocks]

*(volatile unsigned int*)0xE0045FB0 = 0xC5ACCE55; // UNLOCK
*(volatile unsigned int*)0xE0048FB0 = 0xC5ACCE55; // UNLOCK

*(volatile unsigned int*)0xE0045000 = 0x000003FF; // [FUNNEL][CSTF]
*(volatile unsigned int*)0xE0045000 = 0x00000303; // [FUNNEL]
*(volatile unsigned int*)0xE0043000 = 0x000003FF; // [FUNNEL][CSTF]
*(volatile unsigned int*)0xE0043000 = 0x000003FF; // [FUNNEL]

*(volatile unsigned int*)0xE00480F0 = 0x00000002; // [SWO][SPPR] //TPIU_SPPR Select NRZ mode
*(volatile unsigned int*)0xE0048010 = SWOPrescaler;// // [SWO][CODR] //TPIU_ACPR here is 64K Example: 72/48 = 1,5 MHz 0x0000000A;

*(volatile unsigned int*)0xE0000E80 = 0x0001000C; // [ITM][ITM_TCR][Disable ITM]
*(volatile unsigned int*)0xE0000E80 = 0x0001040A; // [ITM][ITM_TCR][Enable DWT->TPIU. Configure timestamp]
*(volatile unsigned int*)0xE0000E80 = 0x0001040B; // [ITM][ITM_TCR][Enable ITM block]
*(volatile unsigned int*)0xE0000E00 = 0x00000001; // [ITM][ITM_TER][Enable stimulus ports]

*(volatile unsigned int*)0xE0000E80 = 0x0001040A; // [ITM][ITM_TCR][Disable ITM]
*(volatile unsigned int*)0xE0000E80 = 0x0001040B; // [ITM][ITM_TCR][Enable ITM block]
*(volatile unsigned int*)0xE0000E00 = 0x00000001; // [ITM][ITM_TER][Enable stimulus ports]
*(volatile unsigned int*)0xE0000E40 = 0x00000008; // [ITM][ITM_TPR][Set privileges]
}

I would appreciate any help in this matter.
Thank you.

[ErichStyger]

Hi @ConstYu ,

see section 'standalone SWO' in https://mcuoneclipse.com/2022/01/24/mcuxpresso-ide-11-5-0/ :

there is a 'SWO and Trace Console' which shows all the register writes for SWO.

Other than that, I describe more SWO features in https://mcuoneclipse.com/2022/07/27/mcuxpresso-ide-11-6-0/ and https://mcuoneclipse.com/2021/07/12/standalone-swo/ :-).

I hope this helps,

Erich

[ErichStyger]

Hi @ConstYu ,

unfortunately, I don't own a RT117x board, so I cannot try it out, and I have not studied the RT11xx family as I'm currently not using it in my designs.

As far as I can tell, the errata is not linked to SWO use case here.

What I would recommend is that you check your clocking and pin muxing: are they working?

I hope this helps,

Erich

[ConstYu]

Hi @ErichStyger 

I checked my clocking and pin mux, didn't find any obvious error, my clock configure is as below, while pin mux should be right, as ITM can work well when use the SWO configure tool to output string.

My code still crashed when access 0Xe0045fb0 when not in debug mode, while runs OK when code runs in debug mode, so MCUXPRESSO may have some additional step, really don’t know which step is missing in this code.

In MCXpresso, it have a option to select “force SWO initialization by IDE“  in below figure1, but I didn’t find what MCXpresso will do when check this option, this option is very important.

/* Configure CSSYS using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_CSSYS_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Cssys, &rootCfg);

/* Configure CSTRACE using SYS_PLL2_CLK */
rootCfg.mux = kCLOCK_CSTRACE_ClockRoot_MuxSysPll2Out;
rootCfg.div = 8; //66M=8 132M=4
CLOCK_SetRootClock(kCLOCK_Root_Cstrace, &rootCfg);

SWO_Init(66000000, 2000000);

[ErichStyger]

Hi @ConstYu ,

In MCXpresso, it have a option to select “force SWO initialization by IDE“ in below figure1, but I didn’t find what MCXpresso will do when check this option, this option is very important.

The IDE should have reported what it does this in the console, as noted in my previous reply.

Erich

[ConstYu]

Hi @ErichStyger ,

Thanks for your advice, you are the god-like man, I study many blog you post, all are very useful. For this topic, based on your guider, I can implement the SWO output on RT1060 demo board when make initialization in application code, it can work well when MCU is not in debug mode. But with same method(using the configuration code generated by MCUXpresso), it still doesn't work on RT117x demo board when MCU is not in debug mode, while using the MCUXpresso embedded SWO configuration tool can work well in debug mode. 

I make some debug, found MCU crashed when operate 0xE0045000 address. 

*(volatile unsigned int*)0xE0045000 = 0x000003FF; // [FUNNEL][CSTF]

below is the initial code I am using, could you help give some advice or make a verify, I suspect there is some initial step is missing.  and there is a RT117X errata called ERR050708: Debug: CoreSight components are not linked to CoreSight ROM table, not sure how we fix it in MCUXpresso.

Thanks in advance.

void SWOOUT_Init(uint32_t cpuCoreFreqHz, uint32_t SWOSpeed) {
volatile uint32_t SWOPrescaler = (cpuCoreFreqHz / SWOSpeed) - 1; /* SWOSpeed in Hz, note that cpuCoreFreqHz is expected to be match the CPU core clock */

/*---------- Enable use of trace and debug blocks (DWT, ITM, ETM, TPIU) ----------*/
*(volatile unsigned int*)0xE000EDFC = 0x01000000; // [DEMCR.TRCENA][Enable trace and debug blocks]
PRINTF("hello world11.\r\n");

/***---------- Configure SWO ----------***/
*(volatile unsigned int*)0xE0045000 = 0x000003FF; // [FUNNEL][CSTF]
PRINTF("hello world111.\r\n");
*(volatile unsigned int*)0xE0045000 = 0x00000303; // [FUNNEL]
PRINTF("hello world1222.\r\n");
*(volatile unsigned int*)0xE0043000 = 0x000003FF; // [FUNNEL][CSTF]
PRINTF("hello world333.\r\n");
*(volatile unsigned int*)0xE0043000 = 0x000003FF; // [FUNNEL]
PRINTF("hello world12.\r\n");
*(volatile unsigned int*)0xE00480F0 = 0x00000002; // [SWO][SPPR] //TPIU_SPPR Select NRZ mode
*(volatile unsigned int*)0xE0048010 = SWOPrescaler;// // [SWO][CODR] //TPIU_ACPR here is 64K Example: 72/48 = 1,5 MHz 0x0000000A;
PRINTF("hello world13.\r\n");
*(volatile unsigned int*)0xE0000E80 = 0x0001000C; // [ITM][ITM_TCR][Disable ITM]
*(volatile unsigned int*)0xE0000E80 = 0x0001040A; // [ITM][ITM_TCR][Enable DWT->TPIU. Configure timestamp]
*(volatile unsigned int*)0xE0000E80 = 0x0001040B; // [ITM][ITM_TCR][Enable ITM block]
*(volatile unsigned int*)0xE0000E00 = 0x00000001; // [ITM][ITM_TER][Enable stimulus ports]
PRINTF("hello world14.\r\n");

/***---------- Enable ITM_TRACE ----------***/
*(volatile unsigned int*)0xE0000E80 = 0x0001040A; // [ITM][ITM_TCR][Disable ITM]
*(volatile unsigned int*)0xE0000E80 = 0x0001040B; // [ITM][ITM_TCR][Enable ITM block]
*(volatile unsigned int*)0xE0000E00 = 0x00000001; // [ITM][ITM_TER][Enable stimulus ports]
*(volatile unsigned int*)0xE0000E40 = 0x00000008; // [ITM][ITM_TPR][Set privileges]
PRINTF("hello world15.\r\n");
}

[viktor_marhansky]

Core-Sight regs. might be locked.
Check:
https://developer.arm.com/documentation/100536/0302/About-the-programmers-model/ATB-funnel-registers...
https://developer.arm.com/documentation/100536/0302/About-the-programmers-model/ATB-funnel-registers...