I have a DSPI driver working, well, mostly, using eDMA with the 4.1.8 kernel from the Rev 2.0 SDK.
It appears that the DMA engine glitches or there is a race condition that causes receive channel to
under flow the FIFO thus corrupting the reveived data. For example (data loopback of 16 frames)
Tx: 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff 10
Rx: 11 22 33 44 44 55 66 77 88 99 aa bb cc dd ee ff (10 is left in the Rx FIFO when the DMA returns)
No errors are reported by either DMA channel od the SPI controller. I fear that this is a silicon bug that
would cause us to drop this processor.
Does anyone have an idea what might be going on. I have before and after register dumps if anyone
is interested.
Thank You.
Greg.
