Vector Table Relocation - for 2nd boot area

[lpcware]

Content originally posted in LPCWare by rc51 on Mon Aug 18 16:58:57 MST 2014
Hello,

For the LPC11u37, the vector table is relocatable.  The following is an extension of this and I am curious if you can direct me to an app note - specifically, can a persistent memory location be set to a specified value by the application and then read and interpreted by the boot loader during the startup sequence after a reset.  The boot loader would execute like it always does only it would also interrogate this designated persistent memory location to determine whether or not to enter into ISP mode or not.  This ISP mode would in essence be triggered by loading the PC w/the address of a section of memory that was a bootloader.

A secondary designated persistent memory location could also be used to tell the boot loader to setup a WD reset to occur after some duration.

Thus, if during ISP (from the second PC address) something happened, the WD would reset the system and the designated memory location not queried.

Thank you.  Rick

[lpcware]

Content originally posted in LPCWare by mc on Sat Apr 11 11:48:00 MST 2015
Hi Chris and rc51,
The LPC11u37 is an ARM Cortex M0  based device. You can remap vector table in SRAM using SYSMEMREMAP register. There is no VTOR in M0 core. As mentioned before in this thread, the LPC11E6x and LPC11U6x are an ARM Cortex M0+ based devices. You can relocate vector table using VTOR. You can also relocate vector table in SRAM using SYSMEMREMAP as shown in below application note.

http://www.lpcware.com/content/nxpfile/an11511-lpc11u6x-application-programming

You can replace SYSMEMREMAP with VTOR in above application note. If you want to place at location NEW_VECT_TBL.

*( volatile unsigned int *)0xE000ED08 = (0xFFFFFF00 & NEW_VECT_TBL);

We will correct CMSIS files.

[lpcware]

Content originally posted in LPCWare by LessThanZero on Fri Apr 10 07:26:26 MST 2015
The NVIC VTOR register is used by the MCU to locate the vector table. With regard to populating the vector table itself, that's left as an exercise. Most people define a separate (e.g. RAM) vector table in a named section, and make sure that section is copied to the desired location.

LessThanZero

[lpcware]

Content originally posted in LPCWare by Chris75 on Fri Apr 10 05:59:39 MST 2015
Hello,

How do I relocate the vector table ?
CMSIS header file for LPC11E6x (version V0.6) states:

#define __VTOR_PRESENT                 0            /*!< Set to 1 if CPU supports Vector Table Offset Register 

I there an other way to relocate the vector table or is this informaties in the CMSIS header file not correct ?

regards,

Chris.

[lpcware]

Content originally posted in LPCWare by xianghuiwang on Fri Jan 09 14:57:22 MST 2015
Hi, rc51,

LPC11u37 as other m0 MCU allows configuring the interrupt vector table to bottom of ram at run time, but not arbitrary location with support from the ROM booloader.

m0+ MCU like LPC11u68 allows configuring the interrupt vector table to an arbitrary location at run time.

regards,