Using WWDT to trigger reset

[lpcware]

Content originally posted in LPCWare by KiloMike on Tue Mar 18 14:34:17 MST 2014
Hi,

I've just started development of new firmware for a project that uses the LPC812 processor. I have the LPCxpresso LPC812 development board and the LPC Link 2 board configured as a SEGGER J-link JTAG. I have experience with several other LPC processors but I have never before used the LPC812.

I am having trouble getting the watchdog timer to start however. I figure I must be missing something subtle but I've been hacking away at it for the past 6 hours and it is time to cry uncle. I found a thread about the WWDT on the LPC4357 processor on these forums but the solution described there doesn't work in my case. Maybe someone here can see what I've done wrong and point me in the right direction?


My reset function is as follows:

void Reset(void)
{
    // enable WDT clock
    SYSAHBCLKCTRL |= 0x00020000;

    // configure the watchdog timer to run at 1 MHz ±40%
    WDTOSCCTRL = 0x00000181;

    // Enable the watchdog clock in the power control register (taking care 
    // to set bits 8:14 as required per user manual paragraph 4.6.32)
    PDRUNCFG = ( (PDRUNCFG & 0x000080BF) | 0x00006D00 );

    // set number of watchdog timer to minimum number of ticks before timeout
    WDTC = 0x000000FF;

    // load WDTC into watchdog timer countdown register
    Watchdog_Feed();

    // enable watchdog timer resets
    WDMOD = 0x00000003; // 0x00000023;

    Watchdog_Feed();

}

and my watchdog feed function is defined as:

static void Watchdog_Feed(void)
{
      WDFEED = 0x000000AA;
      WDFEED = 0x00000055;
}

The watchdog registers are defined in my compiler as:

  #define WDMOD          (*(volatile unsigned long *)0x40004000)
  #define WDTC           (*(volatile unsigned long *)0x40004004)
  #define WDFEED         (*(volatile unsigned long *)0x40004008)
  #define WDTV           (*(volatile unsigned long *)0x4000400C)

And the relevant clock control registers are defined as:

  #define SYSAHBCLKCTRL  (*(volatile unsigned long *)0x40048080)
  #define WDTOSCCTRL     (*(volatile unsigned long *)0x40048024)
  #define PDRUNCFG       (*(volatile unsigned long *)0x40048238)

I have checked the values of the following registers after calling the reset function:

SYSAHBCLKCTRL = 0x0002C15F
WDTOSCCTRL = 0x00000181
PDRUNCFG = 0x0000EDB0
WDTV = 0x00000000
WDMOD = 0x00000000

Notice that WDTV and WDMOD stay stubbornly stuck at 0? Even adding a delay of a few microseconds after calling the reset function doesn't make a difference. Does anyone have any ideas about what I might be missing? If I had to guess, it would be that the feed isn't working properly. I have tried moving the writes to WDFEED around in the code but nothing seems to make a difference.

Thanks in advance!

[lpcware]

Content originally posted in LPCWare by MarcVonWindscooting on Sat Mar 22 07:55:21 MST 2014

---

Quote: LabRat

So obviously 'Chapter 12.6 Table 155. Register overview: Watchdog timer (base address 0x4000 4000)' is wrong...

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because that clashes with MRT !

[lpcware]

Content originally posted in LPCWare by LabRat on Fri Mar 21 17:45:31 MST 2014

---

Quote: KiloMike
The watchdog registers are defined in my compiler as:

  #define WDMOD          (*(volatile unsigned long *)0x40004000)
  #define WDTC           (*(volatile unsigned long *)0x40004004)
  #define WDFEED         (*(volatile unsigned long *)0x40004008)
  #define WDTV           (*(volatile unsigned long *)0x4000400C)

---

:quest:

Datasheet:

http://www.nxp.com/documents/data_sheet/LPC81XM.pdf

Fig.7 is talking about WWDT 0x4000 00000

UM:

http://www.nxp.com/documents/user_manual/UM10601.pdf

Fig.2 is talking about WWDT 0x4000 00000


LPCXpresso is talking about:

#define LPC_APB0_BASE         (0x40000000UL)
/* APB0 peripherals */
#define LPC_WWDT_BASE         (LPC_APB0_BASE + 0x00000)

#define LPC_WWDT              ((LPC_WWDT_TypeDef   *) LPC_WWDT_BASE  )

So obviously 'Chapter 12.6 Table 155. Register overview: Watchdog timer (base address 0x4000 4000)' is wrong...

[lpcware]

Content originally posted in LPCWare by KiloMike on Fri Mar 21 17:13:49 MST 2014
Update:

I put the problem aside for a day or so while developing the rest of my project, but I just had an idea and tried it on a whim before going home today:

Both the LPC81x and LPC1768 processors are ARM Cortex processors. I noticed, however, that the user manual for the LPC81x processor lists the watchdog registers as being located at 0x40004000 plus offsets, while the LPC176x user manual lists the watchdog registers as being located at 0x4000000.

On a hunch, I changed the definitions for the watchdog registers to 0x40000000 plus offsets in my LPC81x project and the watchdog now seems to work! I haven't tested it in any detail other than to see that I can change the amount of time that elapses before the watchdog timer resets the processor. Those tests seem to confirm that I am right.

I think that there is a series of typos in the LPC81x user manual where it lists the memory locations of the watchdog registers.

Maybe someone from NXP could comment?