Content originally posted in LPCWare by Nikhil Durlabhjibhai Dhameliya on Mon May 30 06:24:38 MST 2016 Hi sir,
I would kindly ask for your help concerning a problem on interfacing between the MCB1800 board (LPC1857 single core) and the cam OV7670. I'm working on application "SCT camera interface design with LPC1800 and LPC4300" (AN11365). Below the link where you can download the orignal firmware:
This is Keil project.I have ported this code in LPCXpresso and made some modification in existing code. ->I have removed I2C interface with Camera for READ and Write to SDRAM.Instead i have used FPGA board that works as Camera and directly gives Vsync,HSync and PCLK signals. My configuration are: Active_Pixels_Per_Line ==> 3520 Active_Lines_Per_Image ==> 2000 Clock = 45MHz = 22.22 nS ->I have attached capture image for all the signals.Data signal is provided to 8 GPIO pins starting from 0 to 255 continuously.
ISSUE: One line of Data written to SDRAM at each DMA request for PCLK rise signal. But when i read SDRAM after one line data is completed(HSync goes low from High) then data found missing. kindly check image "Data_READ_SDRAM.png" file for data write on SDRAM.It shows that after 0 on 0x28000500 ram location,directly 2 is written on next ram location 0x28000501.so 1 is missed.
I have same problem ， the data is missing, so the sct flex solution for camera , I think it can not working in high freqency, I tested if >12Mh,then there will be problems.
Content originally posted in LPCWare by Nikhil Durlabhjibhai Dhameliya on Thu Jun 02 00:41:12 MST 2016 I have reduced CLK from 45 MHz to 22.5Mhz but still one byte missing after proper two bytes write to SDRAM... Any suggestion???
Content originally posted in LPCWare by wmues on Mon May 30 13:49:06 MST 2016 I think that your bandwidth requirements are too high for that processor. NXP has a bandwidth calculator spreadsheet. Check it.
