Reserved bits in LPC1317

[lpcware]

Content originally posted in LPCWare by aamir ali on Wed Jul 17 03:41:10 MST 2013
Some of registers says that user should not write 1 to this bit & reading this bit is undefined.

But there are registers like "PDRUNCFG", which says that user should only write 1 for some of its bits. But user manual doesn't say that reading bit is undefined. So does that mean reading this bit is defined always & will return '1'

So which one is correct way of writing to register, suppose I have turn on ADc module:

1. LPC_SYSCON->PDRUNCFG &= ~(1UL<<4);    /* Disable Power down bit to the ADC block. */


2. uint32_t temp;
   temp = LPC_SYSCON->PDRUNCFG & 0x000005FF;   /* mask out reserved bits */
   temp = temp & (~(1UL << 4))                 /* turn on ADC module bit */
   LPC_SYSCON->PDRUNCFG  = temp | 0x0000E800;  /* set bits which need to be high always */

[lpcware]

Content originally posted in LPCWare by cfbsoftware on Mon Jul 22 01:22:57 MST 2013
You have to make sure bits 1, 2, 8 and 9 are cleared if you want I2C. Using the 'SET' data type feature of the Oberon programming language I write it like this:
  VAR
    s: SET;

  SYSTEM.GET(MCU.IOCONPIO04, s);
  SYSTEM.PUT(MCU.IOCONPIO04, s - {1, 2, 8, 9} + {0});

i.e. I get the existing value and then clear bits 1, 2, 8 and 9 and set bit 0 before writing it back again. It looks to me as though you have your bit mask inverted compared to what it should be. I haven't tested it but I believe the equivalent in C is:

LPC_IOCON->PIO0_4 = (LPC_IOCON->PIO0_4 & 0xFFFFFCF9) | BIT_0

[lpcware]

Content originally posted in LPCWare by aamir ali on Sun Jul 21 22:42:44 MST 2013
my mistake I wrote bit1 , its actually BIT0,
so on writing P0.,4 iocon register 0x01 it don't work as I2c pin

[lpcware]

Content originally posted in LPCWare by cfbsoftware on Fri Jul 19 16:35:07 MST 2013
What is BIT_1 defined as? If it is 2 as I would expect then it wouldn't work as bits 1 and 2 are reserved. You need to OR the value 1 (BIT_0?)

[lpcware]

Content originally posted in LPCWare by DF9DQ on Fri Jul 19 06:02:52 MST 2013
I can't confirm your findings.

When I write 0x001 (standard/fast I²C) or 0x0201 (FM+) into the IOCON register for PIO0_4 and PIO0_5, the I²C communication works perfectly.

[lpcware]

Content originally posted in LPCWare by aamir ali on Thu Jul 18 21:00:19 MST 2013
thanks for ur reply.

1 .Now consider a P0.4 & P0.5 iocon registers. Bit 7 denotes analog mode in pins having analog function, writing 0 to bit 7 activates analog mode. But in p0.4 & p0.5 iocon there is no analog mode & these bits are reserved so when I write zero to this bit then pin no more behave like i2c pin.

So to work it as I2c I have to write 1 to this pin.

I have to write like:

LPC_IOCON->PIO0_4 = 0x00000081;    /* pin now works fine */


But if I mask out reserved bits
LPC_IOCON->PIO0_4 = (LPC_IOCON->PIO0_4 & 0x00000307) | BIT_1        /* pin don't behave as I2c pin */


Can you give some insight what exactly to do with reserved bits

[lpcware]

Content originally posted in LPCWare by wellsk on Thu Jul 18 12:04:00 MST 2013
You will have to honor the states the user manual indicates, so the #2 option is your better choice.

For some bits, you'll need to always write a '1' regardless of read value. And others, you'll need to write the read value back.
Generally, if a bit says reserved, I wouldn't trust its value to be 0 or 1 unless the UM specifically says it returns 0 or 1.

For a register like PDRUNCFG and related sleep registers, you'll need to be careful altering bits so they stay in the states the UM designates.
Something like the following code should allow you to enable and disable specific bits while maintaining the correct UM states.

/* PDRUNCFG register mask */
#if defined(CHIP_LPC1347)
#define PDRUNCFGUSEMASK 0x0000E800
#else
#define PDRUNCFGUSEMASK 0x0000F800
#endif
#define PDRUNCFGMASKTMP 0x000005FF

/* Power down one or more blocks or peripherals */
void Chip_SYSCTL_PowerDown(uint32_t powerdownmask)
{
uint32_t pdrun;

pdrun = LPC_SYSCTL->PDRUNCFG & PDRUNCFGMASKTMP;
pdrun |= (powerdownmask & PDRUNCFGMASKTMP);

LPC_SYSCTL->PDRUNCFG = (pdrun | PDRUNCFGUSEMASK);
}

/* Power up one or more blocks or peripherals */
void Chip_SYSCTL_PowerUp(uint32_t powerupmask)
{
uint32_t pdrun;

pdrun = LPC_SYSCTL->PDRUNCFG & PDRUNCFGMASKTMP;
pdrun &= ~(powerupmask & PDRUNCFGMASKTMP);

LPC_SYSCTL->PDRUNCFG = (pdrun | PDRUNCFGUSEMASK);
}

You can get more complete functions specific to these (SYSCON/SYSCTL) registers in the CHIP_13xx sysctl_13xx.h/c file in LPCOpen.