LPCOpen returns wrong dividerIndex for LPC_ETHERNET->MAC.MCFG

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LPCOpen returns wrong dividerIndex for LPC_ETHERNET->MAC.MCFG

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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by qwaszx on Fri Jun 21 04:53:49 MST 2013

In file enet_17xx_40xx.c function:


<em>uint32_t Chip_ENET_FindMIIDiv(LPC_ENET_T *pENET, uint32_t clockRate)</em>


returns <em>(dividerIndex-1)</em> that it should.


For example for System Clock Rate 120MHz and clockRate 2.5MHz it returns 12. This means that clock divider for MDC is 44, and MDC freq = 120 / 44 =  2.73MHz


To correct this issue following table should be changed:


 STATIC const uint8_t EnetClkDiv[] = {<span style="text-decoration: underline;"><em><strong>4,</strong></em></span> 4, 6, 8, 10, 14, 20, 28, 36, 40, 44, 48, 52, 56, 60, 64};


And does anyone know why every "Maximum AHB clock supported" in table 159 of UM10562 "LPC408x/407x User manual" (page 215) equals <em>(divider*2.5)</em>, but for dividers 36,40,44 it equals <em>(divider*2.5 - 10)</em>?

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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by xianghuiwang on Sun Oct 27 11:47:47 MST 2013
Hi, Qwaszx,

Your question: And does anyone know why every "Maximum AHB clock supported" in table 159 of UM10562 "LPC408x/407x User manual" (page 215) equals (divider*2.5), but for dividers 36,40,44 it equals (divider*2.5 - 10)?

It is confirmed that there are some errors in the user manual. The divider values are all correct. However, the Max AHB clock supported are not correctly documented for dividers 36, 40, 44. The Max AHB clock supported should be divider*2.5.

So in this table,
Where it says 80 MHz, it should say 90 MHz.
Where it says 90 MHz, it should say 100 MHz.
Where it says 100 MHz, it should say 110 MHz.

We will correct the sample code correspondingly.

Thanks,
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by xianghuiwang on Sun Oct 20 12:18:08 MST 2013
Hi, Qwaszx,

We are investigating on the possible issue you mentioned. Will update soon.

By the way, the current silicon has an errata on the MII interface. You can review the details on the errata sheet:
http://www.lpcware.com/content/nxpfile/errata-sheet-lpc407x8x-eslpc407x8x

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