Content originally posted in LPCWare by efiLabs on Sat Nov 15 18:37:29 MST 2014
there is already a slightly similar post on the 812, but i want to elaborate on the 824
to set a glitch filter a few things need to happen
1) in order to write to the iocon regs the peripheral clock to the iocon block needs to be enabled
/* Enable the clock to the IOCon Block */
Chip_Clock_EnablePeriphClock (SYSCTL_CLOCK_IOCON) ;
2) set the S_MODE (sample mode) bits to the desired IOCONFILTR_PCLK) count
Chip_IOCON_PinSetSampleMode (LPC_IOCON, IOCON_PIO15, PIN_SMODE_CYC3) ;
3) set the desired IOCON glitch filter clock divider registers 6 to 0 (IOCONFILTCLKDIVx) to the desired IOCONFILTR_PCLK ... please observe the numbering of 6 to 0
Chip_IOCON_PinSetClockDivisor (LPC_IOCON, IOCON_PIO15, IOCONCLKDIV0) ;
4) now that the iocon regs are set the peripheral clock can be turned off again
/* Disable the clock to the IOCon Block */
Chip_Clock_DisablePeriphClock (SYSCTL_CLOCK_IOCON) ;
5) and this is the tricky part now ... remember that the IOCONFILTCLKDIVx regs are in descending order of 6 to 0 (outlined in item 3)
LPC_SYSCTL->IOCONCLKDIV[6] = 0x00ff ;/* IoConClkDiv - 0 = div 255*/
IOCONCLKDIV[6] is IOCON glitch filter clock divider register 0 and NOT 6
6) note that "typedef enum CHIP_PIN_CLKDIV { ..." can only be used for setting the IOCON clock divisor field bits 15 - 13 in the PIO0_xx regs
and can NOT be used as index into the 7 IOCONCLKDIV[index] regs
i wish there would be an enum for the indexing in the 7 IOCONCLKDIV[x] regs to really show this reverse order of reg index vs reg number
7) on top of it if you try to look at the IOCONCLKDIV[x] regs in xpresso, all you see is IOCONCLKDIV6 and no 5 - 0 ... maybe the xpresso guys will read this and try to fix it in the next revision
cheers efiLabs
