Hello,
I'm creating a custom board to test the LPC5526JBD64 microcontroller.
The datasheet shows a schematic for using the internal DCDC converter:
This schematic does not show a connection to an external power supply. More specifically, VBAT_DCDC and VBAT_PMU are connected only to each other and a set of decoupling capacitors (C2, C3, C4, all with different capacities). VDD_PMU has no decoupling capacitors connected to it (I assume that C1 is rather the DCDC converter output filter capacitor).
The AN13033 "Hardware Design Guidelines for LPC55(S)xx Microcontrollers" shows on page 4:
Here, the external power supply 3V3_CORE is connected to VBAT_DCDC and VBAT_PMU. Decoupling is done only over 100 nF capacitors (C21, C26, C27). Further, this schematic shows a set of decoupling capacitors (C11, C12, C13) with different capacities applied to the VDD_PMU pin (again I assume that C14 is rather DCDC converter output filter capacitor).
Now my questions:
- Where should I connect the external 3V3 power supply to?
- What is the proper decoupling of VDD_PMU and VBAT_PMU?
Thanks!
Hi, Daniel,
Q1)Where should I connect the external 3V3 power supply to?
>>>>I do not know the power supply voltage you have, for example if you have 5C DC power supply, you can use a regulator(LDO) to generate 3.3V power supply. This is the 5V to 3.3V converter circuit on LPC55S69-EVK.
But for the 3.3V power supply rail, you have to connect a large capacitor, which dependent on the current. In the case, it is two 10uF caps C50, C51
Q2)What is the proper decoupling of VDD_PMU and VBAT_PMU?
>>>For the VBAT_PMU, there are three pin are connected to the 3.3V power rail, VBAT_PMU pin(pin 51), two VBAT_DCDC(pin49,50), each pin requires a 100nF decoupling capacitor which should be as close as possible to the power pin on PCB, so there are three caps C21,C26 and C27.
For the VDD_PMU, it is another story, because this is part of the DC/DC converter, on the VDD_PMU, you have to connect a 22uF capacitor and 4.7uF inductor as the Fig 4 from data sheet of LPC55xx, the capacitor takes effect on the ripple voltage on the VDD_PMU pin from theory, but you can not increase or decrease the capacitor, which is computed from switch frequency and ripple voltage spec in advance. But is okay to add 100nF cap on the VDD_PMU as decoupling cap.
In conclusion, for the VDD_PMU caps, pls only refer to the data sheet spec.
Hope it can help you
BR
XiangJun Rong
Hi XiangJun Rong,
Thanks for sharing your experience and opinion. I'm also favoring the configuration of Fig. 2 over Figure 4. because usually there should be at least a single decoupling capacitor for each supply pin and Fig. 2 is clearly adhering to that principle where Fig. 4 is not.
Did I already mention that I hate it when specification documents contradict each other. I found another document describing the connections concerning built-in DCDC converter: AN12325.pdf
Compare this schematics to earlier Fig. 4., a single decoupling capacitor C5 has been added to VDD_PMU (in addition to the output capacitor C1).
The application note continues with a PCB guide line, i.e. how to layout the components related to the DCDC converter (Fig. 1) on the PCB. The suggested PCB layout looks like this:
For improved readability I've added the relevant net labels. As you can see, capacitors labeled (white text color) C2-C4 decouple VBAT_DCDC. However, on the PCB there's also a set of decoupling capacitors for VBAT_PMU, i.e. (yellow text color) C3, C7 and C9. Those are not shown in the schematics.
Further, C1 and C5 seem labeled wrong.
In the schematics, C1 is the 22 uF output capacitor to GND. In the PCB layout, the component labeled C1 is connecting VBAT_PMU and VBAT_DCDC. I assume it's a ferrite bead instead. I think that in the PCB layout the capacitor C5 should be labeled C1.
Now where's C5 from the schematics? While the PCB snippet does not show how FB and L1 are connected to VDD_PMU, one can assume that there's also a set of decoupling capacitors at VDD_PMU, e.g. C12 and neighbours. Those replace the single decoupling capacitor C5 in the schematics.
Please NXP, write design guides, specs and app notes that are consistent.
Hi @devel
Why do you think that the combination of different decoupling capacitors is silly and what do you recommend instead?
I've seen this decoupling scheme (using a set of uF/nF/pF capacitors on a single supply pin) on other layouts as well. For example it is used on the LPCXpresso55S28 board.
That's what I came up with:
Edit: For the 4.7 uH inductor L1 I'm using a Würth Elektronik WE-TPC inductor, order no. 744025004 : Ir=1.35 A, Isat = 1.7 A, fres = 84 MHz.
Hi, all
I have checked with AE team, for the by-pass decoupling capacitors for pin VBAT_PMU and VBAT_DCDC pins, the Fig 4 in data sheet has to be followed up, the caps are given and reviewed by design team. Because this is a DC/DC converter input stage, so the caps do not follow up the general regulation.
BR
XiangJun Rong
