LPC55xx ADC timer trigger

[_Ferrari_]

Dear all,

In my project I have to  use hardware triggers to start ADC conversion.

In the LPC5526JBD64_User_Manual_11126.pdf I read:

"When a hardware trigger input is enabled, hardware trigger events are detected on the
rising-edge of the associated hardware trigger source. The hardware trigger event must
be high for 1.5 ADCK cycles."

It is very clear: if I use an external trigger it is asserted only on rising-edge.

But it is not so clear if it is the same for internal trigger (es State Counter Timer (CTIMER) ct0_mat3_out; trigger 5). It seems that ADC conversion starts every two ct0_mat3_out events.

Could you, please, explain better ?

thank you for you help and cooperation

best regards

[craigmcqueenir]

I had the same question. But I didn't want to use the "toggle" of the output. I was able to set up the CTIMER MAT3 output in PWM mode.

• Put the desired time interval into the MR[0] register.
• Put 1 in the MR[3] register.
• In the MCR register, set the MR0R bit.
• In PWMC register, set the PWMEN3 bit.

The MAT3 output should turn on when the TC == 1 (which is MR[3]), and off when TC == MR[0], and TC is reset to zero at the same time.

[danielholala · Accepted solution]

Hi,

I think this part of the ADC documentation is abundantly unclear. I had a hard time relating the number of the hardware trigger source with the number of the trigger control register (e.g., TCTRL9 is invariably associated with external match register 3 of CTIMER4).

To answer your question, yes, a hardware source triggers only on the positive edge (e.g. when the respective bit in external match register EMR changes from 0 to 1). Thus if you configure EMR[EMC3] timer to toggle this bit, this will effectively double the cycle time.