LPC1857 NVIC Priority Registers

[lpcware]

Content originally posted in LPCWare by SteveO on Wed Apr 15 16:49:49 MST 2015
Having difficulty figuring out the NVIC interrupt priority registers on the LPC1857.  I'm not using CMSIS or other library code.

The LPC1857 User Manual (rev 2.6) says the NVIC supports 53 vectored interrupts.  Table 73 shows eight priority registers (IPR0-IPR7).  According to Table 73, "Each register contains the 3-bit priority fields for 4 interrupts."  8 * 4 = 32, which is less than the 53 interrupts supported by the chip.

I peeked at CMSIS and other library code, and it looks like there are really more than 8 NVIC IPR registers.   I think there are really registers IPR0-IPR13 and the datasheet is wrong where it says there is only IPR0-IPR7.  Can anyone confirm this?

[lpcware]

Content originally posted in LPCWare by starblue on Thu Apr 16 06:35:31 MST 2015

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Quote: SteveO
I have discovered it is possible to write and read back as high as IPR15.  IPR16 and higher do not seem to be implemented.

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Yes, interrupts are implemented in groups of 32 (mostly). There is a register ICTR which tells you how many groups there are, see "ARM v7-M Architecture Reference Manual" DDI0403.

And from "The Definitive Guide to ARM Cortex -M3 and Cortex-M4 Processors", 3rd Edition by Joseph Yiu:
"you can obtain the exact number of interrupts available by writing to interrupt control registers such as interrupt enable/pending registers while the PRIMASK register is set (to disable the interrupt from taking place), and read back to see exactly how many bits are implemented in the interrupt enable/pending registers."

[lpcware]

Content originally posted in LPCWare by SteveO on Thu Apr 16 05:53:30 MST 2015
Thanks for the link.  I calculated that IPR0-IPR13 would be needed to support the interrupts implemented on the LPC1857.  Using a JTAG debugger, I have discovered it is possible to write and read back as high as IPR15.  IPR16 and higher do not seem to be implemented.

It would be good for NXP to correct Table 73 in the next revision of UM10430.

[lpcware]

Content originally posted in LPCWare by starblue on Wed Apr 15 23:35:09 MST 2015
The NVIC is part of the core, so you should better look at ARM documentation for that:
http://infocenter.arm.com/help/topic/com.arm.doc.dui0552a/Cihgjeed.html

In a nutshell, there are up to 60 of these registers for up to 240 interrupts.

Personally I prefer CMSIS functions for core functionality like this, it is standardized across Cortex-M and works well in my experience.