LPC1812 - can't program

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

LPC1812 - can't program

676 Views
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by robertpalmerjr on Thu May 15 15:18:43 MST 2014
Has anyone used the LPC1812 part with LPCXpresso or FlashMagic?

I've spent a couple of days now trying to read and program brand new LPC1812 (two of them actually - both give same results).  I believe it is a documentation/silicon error.  Here are my experiments:

This is a custom board with a 12Mhz LPC1812 part on it.  I have the ISP accessible.

Starting with a brand new part...

TEST #1
Enabling ISP and using FlashMagic:
CRP shows Level 1
Device ID is correctly read and returns the correct value
all other commands (including complete erase) FAIL

TEST #2
Enable ISP and using a Terminal (arrows are informational only):
--> ?
<-- Synchronized
--> Synchronized
<-- OK
--> 12000
<-- OK
--> U 23130
<-- 0
--> P 0 14 0     <-- prepare sectors 0-14 in bank 0 (supposed to be Bank A)
<-- 7                <-- invalid sector
--> P 0 14 1     <-- prepare sectors 0-14 in bank 1 (supposed to be Bank B, but 1812 doesn't have Bank B)
<-- 0                <-- success
--> E 0 14 1
<-- 0

Further...
R 436208380 4   <-- this is address 0x1A0002FC (CRP address for BANK A)
1                        <-- Error Invalid Command
R 452985596 4   <-- this is address 0x1B0002FC (CRP address for BANK B)
0                        <-- success and the uuencoded data below is FF FF FF FF
$________
1020

Based on this testing, I would say that either the 1812 ONLY has Bank B, (data sheet says ONLY BANK A) OR the ISP for this part is using the wrong number to access Bank A (1 instead of the documented 0).

Bottom line is that both LPCXpresso and FlashMagic seem to be using '0' for the bank number which of course fails.  Is there an quick way I can modify one of the connection scripts/programming scripts for LPCXpresso to test this theory?  I have already tried just modifying the FLASH base address in the memory configuration for the part.  While that does correctly fix the linker output, it doesn't seem to have any effect on the SWD connection scripts or flash programming process.  I still get:

Found chip XML file in /Volumes/.../Debug/LPC1812.xml
(  5) Remote configuration complete
( 15) nSRST assert (if available)
Failed on connect: Ep(01). Target marked as not debuggable.
Connected. Was: None. DpID:     EDB6. Info: FTWN9IJGA

Labels (1)
0 Kudos
10 Replies

598 Views
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by robertpalmerjr on Wed May 21 09:59:45 MST 2014
Re-read the thread.  Apparently this batch of LPC1812 has the flash in BANK B, not BANK A.  The default driver assumes the BANK A.  The driver specified is similar, but uses BANK B.
0 Kudos

598 Views
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by TheFallGuy on Wed May 21 08:24:06 MST 2014
Why are you using the wrong flash driver? Surely you should be using the default (LPC18x2_43x2_512.cfx).
0 Kudos

598 Views
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by robertpalmerjr on Wed May 21 07:46:35 MST 2014
It wasn't, but it will now.  I originally had DBGEN pulled LOW which is for boundary scan JTAG.  It is now pulled high so debug should work correctly.  I am now able to erase the part using the SWD port, but I still cannot debug.  I'm using the Flash Driver: LPC18x7_43x7_2x512_BootB.cfx

I keep getting an error about a timeout programming sector 15 (of course the LPC1812 only has sector 0-14).

Ni: LPCXpresso Debug Driver v7.0 (Mar 26 2014 18:33:08 - crt_emu_lpc18_43_nxp build 1243)
Pc: (  0) Reading remote configuration
Nc: Found chip XML file in /Volumes/...Debug/LPC1812.xml

Pc: (  5) Remote configuration complete
Pc: ( 30) Emulator Connected
Xl:
Xc:
Pc: ( 40) Debug Halt
Pc: ( 50) CPU ID
Nc: Emu(2): Conn&Reset. DpID: 2BA01477. Info: FTWN9IJGA
Nc: SWD Frequency: 250 KHz. RTCK: False. Vector catch: False.
Nc: Packet delay: 0  Poll delay: 0.
Nc: Loaded LPC18x7_43x7_2x512_BootB.cfx: LPC18x7/LPC43x7 Flash 2x512KB @0x1A000000 (Boot Bank B) Jul 22 2013 10:38:26  On-chip Flash Memory

Nc: NXP: LPC1812  Part ID: 0x00000000
Pc: ( 65) Chip Setup Complete
Nt: Connected: was_reset=false. was_stopped=false
Cr:v LPCXpresso Free License - Download limit is 256K
Pc: ( 70) License Check Complete
Nt: Loading ELF file 'myapp.axf' at location 1B000000
[color=#f00]Nt: Writing 13396 bytes to 1B000000 in Flash (assumed clock: 288.0MHz)
Pb: 1 of 1 (  0) Writing pages 15-16 at 0x1B000000 with 13396 bytes
Ps: (  0) Page 15 at 1B000000
Ec: Flash driver "ProgramPage" timeout (3000 ms)  PC: 1040018A
[/color]
Pb: (100) Writing Flash ended with an error.
Ed:05: File 'myapp.axf' load failure: Ef(30). Timed-out programming flash.
Nc: Core reset only (VECTRESET)
0 Kudos

598 Views
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by fruitmans on Wed May 21 07:32:37 MST 2014
Hello Ken,

I think we have the same problem as Robert.

We also use the LPC1812JET100.

Markings on the chip:

LPC 12812 JET 100
PMB 607.00 03
ESD 13050-

Data provided by Flash Magic:

Device ID: 0xF00BDB3F
Bootloader version: 12.1

*Addition: Both JTAG and SWD do not work for me.

With kind regards,

Rik

0 Kudos

598 Views
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by mc on Tue May 20 12:22:03 MST 2014
Hi Rob,
Does debugger connect to target through SWD connector?
0 Kudos

598 Views
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by robertpalmerjr on Fri May 16 09:16:55 MST 2014
Already posted.  Looks like my answer and your request passed in the ether
0 Kudos

598 Views
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by usb10185 on Fri May 16 07:12:35 MST 2014
Hi Robert,

Looks like you have carried out a thorough analysis!
There were some early sample parts that had a configuration issue and shipped with Bank B Flash instead of Bank B.
Can you share the part markings so we can correlate?

Thanks,
Ken
0 Kudos

598 Views
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by robertpalmerjr on Fri May 16 06:04:38 MST 2014
Markings on both parts:

LPC1812JET100
PMB607.00     03
ESD13050-
0 Kudos

598 Views
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by lpcxpresso-support on Fri May 16 02:10:38 MST 2014

Quote: robertpalmerjr

Found chip XML file in /Volumes/.../Debug/LPC1812.xml
(  5) Remote configuration complete
( 15) nSRST assert (if available)
Failed on connect: Ep(01). Target marked as not debuggable.
Connected. Was: None. DpID:     EDB6. Info: FTWN9IJGA



Information on this error can be found at:

http://www.lpcware.com/content/faq/lpcxpresso/target-marked-not-debuggable

Regards,
LPCXpresso Support
0 Kudos

598 Views
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by embd02161991 on Thu May 15 20:42:14 MST 2014
Hi Robert,

Can you please send  the package marking  of both the chips ?

Thanks,
NXP Technical Support
0 Kudos