Issue of execution speed in EMC memory

[lpcware]

Content originally posted in LPCWare by hostlin on Wed Feb 06 06:04:05 MST 2013
Hi all,
Please kindly help to check this issue.

I wrote a simple code to test the execution speed in internal RAM, external Flash, and external SRAM of LPC1850.
Just toggle the GPIO output to generate the square wave and measure the period. The result is listed below:

Platform : LPC1850
EMC Bus : CS0 16-bit NOR Flash (S29GL06490N, access time=90ns)
          CS1 16-bit SRAM (CY62187EV30LL, access time=60ns)
          (Due to limitation of customized design, it's unable to implement 32-bit data bus.)
Compiler : IAR EWARM
BASE_M3_CLK = 72 MHz (XOSC=12MHz, PLL1=6)
EMC_M3_CLK = 72 MHz
EMC_CLK_DIV = 0 (not divided. CREG6 is not configured, keeps default value after reset)
EMCControl = 0x00000001
EMCStaticConfig0 = 0x00080001    //16-bit, buffer=enable. Page mode=disable (not supported by S29GL06490N). Extended wait=disable
EMCStaticWaitWen0 = 0x00000000   //CS0 to write enable delay = 0
EMCStaticWaitOen0 = 0x00000000   //CS0 to output enable delay = 0
EMCStaticWaitRd0 = 0x00000007    //CS0 to read access delay = 7 clock cycles
EMCStaticWaitWr0 = 0x0000001F    //CS0 to write access delay = 31 clock cycle (default after reset. The test is only related to read access.)
EMCStaticWaitTurn0 = 0x00000001  //Bus turn around cycles = 1

Compiler optimization = Disable.
measured pulse period = (1) 2.45 us    executed in internal RAM
                        (2) 21.2 us                SRAM via EMC.........8.6 times of (1)
                        (3) 28.5 us                NOR Flash via EMC.....11 times of (1)
The code execution speed in EMC memory is incredibly slow.
A simple GPIO action takes almost 30 us is definitly unacceptable.
Is the result reasonable? Any problems of the settings?

Thanks,
Willie Lin

[lpcware]

Content originally posted in LPCWare by homgin on Wed Feb 20 10:03:51 MST 2013
Hello,
I got the same question.
After surfing the related topics about EMC of LPC18xx,
I know that to run code on SPI quad flash get better performance than external NOR flash.
But considering the power consumption and data backup problem, I have to use asynchronous SRAM instead of SDRAM.
And I did the following test:
LPC1850,system clock = 72MHz,16-bit SRAM(Cypress CY62187, 60ns, page mode supported) in EMC CS1.
Call memcpy() to copy 1MB data in the EMC SRAM.
The code ran on internal SRAM.

uint32 Memptr1=0x1D000000;
uint32 Memptr2=0x1D100000;
for(i=0; i<32; i++)
{
    memcpy((void*)Memptr1, (void*)Memptr2, 0x8000); //copy 32k Byte data
    Memptr1+=0x8000;
    Memptr2+=0x8000;
}

It took almost 350ms to finish the operation and not fit my demand.
The same test I did in STM32F103 which ran at 56MHz with the same SRAM only took 120ms.
I want to know if 2 16-bit SRAMs are connected to CS1 to form the 32-bit bus can double the accessing speed in this case?

Thank you very much.

Homgin

[lpcware]

Content originally posted in LPCWare by nxp21346 on Thu Feb 07 12:29:00 MST 2013
Execution is much faster on internal SRAM because it operates at the full CPU speed (up to 180 MHz) and is 32-bits wide you are only using 16-bit wide external memory that can only operate at 16.6 MHz (1 / 60 ns). For faster performance, since you cannot use 32-bit memory, look for faster external memories (particularly for the SRAM) and also see if you can find a flash memory that supports page mode.

Also check your optimizer settings, using -O3 and enabling optimization for speed should help.

-Dave @ NXP

[priyankb]

Hi Dave,

I am facing same problem on custom board with LPC4088 which run program from EMC Nor flash. Unfortunately we cannot change from flash to sram. Although I have tried using optimization & it works too but the problem is we are using LCD with emWin library & it does not run when optimization applied. So I have ordered a pin compatible flash with page read mode.

I have a question though. In many discussion I have read that as clock speed increases the external memory slows down & I have experienced it but did not understand. Do you have any idea about it?

As I decrease clock frequency EMC Nor flash execution actually speeds up.(24 MHz gives best speed)

Thank you.

Priyank.

[lpcware]

Content originally posted in LPCWare by wmues on Wed Feb 06 08:27:49 MST 2013
What have you expected?

You have used two slow memories. Your compiler has generated slow code (2.45us are 176 cycles).

If you have used SDRAM or serial Flash, it would be faster because of reading the data in burst mode.

And check the output of your compiler!