Code example to run M0+ from FLASH on LPCXpresso

[lpcware]

Content originally posted in LPCWare by filartrix on Tue Jun 30 09:50:52 MST 2015
Hi all,
I have interest in running the code for M0+ from Flash Memory.
I've found in the AN11609 the code for Keil uVision to run the M0+ code from Fash, but the same example is not available for LPCXpresso.
The idea is to store the code for the M0 in a different location and then let the M4 boot the M0 properly.
I'm not sure If I can create a dual core project and how to:
• Provide a reset handler start address to the Cortex-M0+
• Provide a stack pointer address to the Cortex-M0+
[img]http://i.imgur.com/XJzqGAY.png[/img]
Does anyone has a project for LPCXpresso, or some tips?
Thanks
Filippo

[lpcware]

Content originally posted in LPCWare by filartrix on Fri Jul 10 06:17:17 MST 2015
Thanks for your support!
your solution is working.
Filippo

[lpcware]

Content originally posted in LPCWare by lpcxpresso-support on Wed Jul 08 02:07:00 MST 2015
OK, I can see the problem - there is a subtle issue with the managed multicore linker script generated for the in the master M4 project  that normally doesn't trigger any problems, but is for you. Put the .ld file from the attached ZIP file into a 'linkscripts' subdirectory of the M4 master project and this should fix the issue for now. And we'll fix it properly for the next LPCXpresso release.

Note that you do need to fix the MCU memory configuration for the master M4 project that you have checked into your repository so that the RAM64 is listed as the second RAM block in that project. As per this screenshot:

[img]http://www.lpcware.com/system/files/lpc54_master_ram.png[/img]

Regards,
LPCXpresso Support

[lpcware]

Content originally posted in LPCWare by filartrix on Tue Jul 07 09:28:15 MST 2015
The problem i that when I run the code from debugger it works ( I can green LED toggling), but when I exit from debug session, detach the USB cable and reconnect it, the board goes in hard fault (red LED).

[lpcware]

Content originally posted in LPCWare by lpcxpresso-support on Mon Jul 06 10:33:57 MST 2015
So, what happened? Does it work? If not, describe what theproblem is.

[lpcware]

Content originally posted in LPCWare by filartrix on Mon Jul 06 10:24:19 MST 2015
0:) ops, I was using semihosting...
but then I removed references to printf and semohosting.
I also tried to recompile the code removing semihosting libraries
the code is here:
https://bitbucket.org/fcasamassima/nxp_lpc54102_sensorboard/src
[img=608x560]http://i.imgur.com/7iob4PH.png[/img]

[lpcware]

Content originally posted in LPCWare by lpcxpresso-support on Mon Jul 06 08:11:14 MST 2015
You don't have any semihosted code (like printf's) in your applications, do you?

[list]
  [*]http://www.lpcware.com/content/faq/lpcxpresso/semihosting
[/list]
If that isn't it, then can you post your actual projects

[list]
  [*]http://www.lpcware.com/content/faq/lpcxpresso/how-importexport-projects
[/list]
or at least ZIP up and post the map files generated by the linker (for both the M4 and M0 projects) ?


Regards,
LPCXpresso Support

[lpcware]

Content originally posted in LPCWare by filartrix on Mon Jul 06 07:55:41 MST 2015
Hi, thanks for your help, I tried your solution, but I still have an issue:
When Debugging the code works perfectly, as expected, but when the board starts again(disconnect and reconnect power supply) the MCU goes in Hard Fault. I thought that the problem was due to my code but it was too strange, the exact same code was running in debug and generated hard fault after reset.
I tried the exact same code with different optimization levels: when the code for M0+ is 39Kb an Hard fault is generated , with optimization the code is 24Kb and no Hard fault is generated.
Here's a summary:
Purpose: use the RAM0 for Program meory of M0+.
Solution: see your previous post
Problem: when the code to be loaded on M0+ is greater than 32Kb the program goes in "hard fault" after a reset. if the code is executed from debugger, it works correctly.

M0+ Memory config.
[img]http://i.imgur.com/eJjE2g5.png[/img]

M4 Memory config
[img]http://i.imgur.com/nnOjfBd.png[/img]

M4 Multicore Settings
[img]http://i.imgur.com/UmhZfvF.png[/img]

[lpcware]

Content originally posted in LPCWare by lpcxpresso-support on Thu Jul 02 00:47:37 MST 2015
You certainly should be able to use the 64KB RAM block for the M0 image. This will involve modifying both the M0 memory configuration (so that only the 64KB block is used instead of the 32KB block) and the M4 memory configuration (so that the 32KB block is listed first rather than second).

After doing that you will also need to modify the M4 linker properties so that the M4 master places the M0 code into the 64KB RAM block:

[img]http://www.lpcware.com/system/files/multicore_ram.jpg[/img]

Regards,
LPCXpresso Support

[lpcware]

Content originally posted in LPCWare by filartrix on Wed Jul 01 10:54:28 MST 2015
Thank you for your answer,
I'm aware that for most applications is better to run M0 code from SRAM, but unfortnately my code does not fit in the 32Kb of bank 1.
In my scenario, the M4 boots the M0 and the the M4 is set to sleep and has a very relaxed duty cycle.
I also tried to assign Bank 0 to M0 and Bank 1 to M4, but this even more trickier than run M0 from Flash.

[lpcware]

Content originally posted in LPCWare by lpcxpresso-support on Wed Jul 01 00:12:19 MST 2015
I suggest you don't. The LPCXpresso multicore support is setup in the way it is (as detailed in http://www.lpcware.com/content/faq/lpcxpresso/lpc541xx-multicore-apps) for very good reasons. See http://www.lpcware.com/content/forum/running-flash-code-both-cores

Regards,
LPCXpresso Support