twrk60d100 ethernet

[davidsherman]

Hello, I am using the twrk60d100 with the twr-ser module to use the ethernet.  I have jumpered the boards according to the documentation to use the RMII mode, and I've confirmed that the OSCERCLK is 50 MHz by routing it to PTC3. What is strange is the MDC clock is very jittery and it's far off from the expected value.  If the OSCERCLK is 50 MHz, is this what is meant by the "module clock"?  If I put in a value of 9 in the ENET_MSCR register for the MII_SPEED, the MDC clock is around 4 MHz as I've observed.

The core clock is 100 MHz.

If I put in a value of19, then I get something more like 2.5 MHz for the MDC, but it's still very unstable.  What am I missing?

[mjbcswitzerland · Accepted solution]

Hi David

The calculation of the MIIM clock value is:
MSCR = (((ETHERNET_CONTROLLER_CLOCK/(2 * MII_MANAGEMENT_CLOCK_SPEED)) + 1) << 1); // generate the communication channel clock

where the ETHERNET_CONTROLLER_CLOCK is the core clock (eg. 96MHz when the PLL is set to allow the maximum clock speed compatible with USB operation) and MII_MANAGEMENT_CLOCK_SPEED is the speed you are aiming at.

Eg. to generate 800kHz MIIM clock a value of 0x7a would be used. Typically 2.5Mz is max. that the PHY will accept (although some allow higher) and a value of 4 would be about 24MHz and thus much too high.

Try the binary here, which sets 800kHz:

http://www.utasker.com/kinetis/TWR-K60D100M.html

Beware that there tend to be only weak pull-ups on the lines and, due to the tower kit back plane capacitance, the signal swing is slow (they are open-drain and should have much stronger pull-ups). Using frequencies of the more standard 2.5MHz is not recommended since it becomes unreliable (only about 1V of signal swing) so this is why a slow clock is recommended (and in fact necessary).

Regards

Mark

[davidsherman]

Thank you Mark, I believe that answered my question.  It did appear to be using something in the neighborhood of 100 MHz for the module clock, although the jitter in the frequency pointed to a problem with the system clock, so I've fixed that.