Kinetis K-10 Interrupt latency question.

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Kinetis K-10 Interrupt latency question.

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anatolyodler
Contributor I

Hello, all.

We're working with Kinetis K-10 MCU. No operating system.

What is the interrupt latency of the context switch between an background thread (main function) and PIT interrupt?

What happens, if other interrupt, with higher priority that the PIT, enters in the middle of that context switch?

Thank you.

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2 Replies

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deepakrana
NXP Employee
NXP Employee

hi

For the cortex M interrupt handling the ARM info centre gives the best information and is part of their documentation. The interrupt handling for all Cortex M series is under ARM control.

More info on the interrupts check this link:

ARM Information Center 

There are two important concepts in interrupt handling of cortex M - tail chaining and later arrival concept

This you can check at link

ARM Information Center

You need to right click on these links to open the right link under the name shown.

The above should help with all the questions that you have asked.

560 Views
deepakrana
NXP Employee
NXP Employee

hi

hope this helped in you understanding of your problem