Kinetis FlexCAN transmit mailbox in strongly order like FIFO or circular buffer

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Kinetis FlexCAN transmit mailbox in strongly order like FIFO or circular buffer

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henrynguyen
Contributor IV

Hello,

we have a requirements as:

1- utilize more than 1 MB for transmission, let's say my MB 8 to MB 15 are available for TX.

2- as soon as 1 of the TX MB(x) is available (e.g. corresponding IFLAG1 bit  is set), interrupt happens, our codes can load another data set to this MB for transmission.  we do not want to wait until all setup MB completely done with the transfer to reload the next MB.  

3- In our case, we have a large (e.g. 100-byte message) that got broken down into multiple 8-byte CAN packets.  Each of them will have the same CAN header except the last 2 bits.  the first CAN packet header will have last 2 LSB bits as 01, then all middle packets' CAN header will have last 2 LSB bits as 10 and the last packet CAN header has last 2 LSB bits as 11.

4- we need to transmit these packets (#3 above) in fixed order.  Otherwise, we have CRC error in the receiving end.

Now, FlexCAN provides 2 control bits for MB transmission, CTRL1[LBUF] and MCR[LPRIOEN].

Reading on these 2 things, I still can not see how we can force the FlexCAN to transmit in the circular buffer or FIFO fashion to strongly order transmission.

can you please let us know if we misunderstand something?

here is our understanding:

if CTRL1[LBUF] = 1, that means the FlexCAN always scan from MB 8 to 15.  whichever is active, will be transferred first.  For example, if i have data ready in MB 8, 9, 10, 11, then MB8 will transfer first, MB9 is next and so on.  Let assume, IFLAG1[8] = 1 or IFLAG1[9] = 1 triggers the interrupt and mean while FlexCAN is transmitting MB10, then, we can fill next data to be transfer to MB8 and MB9.  Then let's say FlexCAN just completes MB10 and it sees MB8, MB9 active again, it will transfer MB8 first without transferring MB11.  Is that correct?

if CTRL1[LBUF] = 0 and MCR[LPRIOEN] = 0, assume we use Ext Frame, our understanding is that it looks at full 32-bit CAN header and compare.  whichever one has the lowest arbitration value (lowest 32-bit value) this will be transfer first.  if 2 MB having the same CAN header, then, the lower MB number win arbitration (say MB8 and MB9 have the same lowest arbitration value, then MB8 is the winner).  is that correct?  In our case, we have a large (e.g. 100-byte message) that got broken down into multiple 8-byte CAN packets.  Each of them will have the same CAN header except the last 2 bits.  the first packet will have LSB bits as 01, then all middle packets have LSB bits as 10 and the last packet has LSB bits as 11.  in this example, i am not even sure how the flexcan can for sure send in strongly order.

if CTRL1[LBUF] = 0 and MCR[LPRIOEN] = 1, can you please clarify how 3-bit PRIO field is determined for arbitration?

Thanks and Best Regards,

Henry Nguyen

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756 Views
henrynguyen
Contributor IV

hello NXP support team, 

can you please provide some inputs?

thanks and Beat Regards 

Henry Nguyen 

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