It's supported to switch to the FEI from the FEE, and I've attached the code as below, please for details.
int fll_freq(int fll_ref)
{
int fll_freq_hz;
if (MCG_C4 & MCG_C4_DMX32_MASK) // if DMX32 set
{
switch ((MCG_C4 & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT) // determine multiplier based on DRS
{
case 0:
fll_freq_hz = (fll_ref * 732);
if (fll_freq_hz < 20000000) {return 0x33;}
else if (fll_freq_hz > 25000000) {return 0x34;}
break;
case 1:
fll_freq_hz = (fll_ref * 1464);
if (fll_freq_hz < 40000000) {return 0x35;}
else if (fll_freq_hz > 50000000) {return 0x36;}
break;
case 2:
fll_freq_hz = (fll_ref * 2197);
if (fll_freq_hz < 60000000) {return 0x37;}
else if (fll_freq_hz > 75000000) {return 0x38;}
break;
case 3:
fll_freq_hz = (fll_ref * 2929);
if (fll_freq_hz < 80000000) {return 0x39;}
else if (fll_freq_hz > 100000000) {return 0x3A;}
break;
}
}
else // if DMX32 = 0
{
switch ((MCG_C4 & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT) // determine multiplier based on DRS
{
case 0:
fll_freq_hz = (fll_ref * 640);
if (fll_freq_hz < 20000000) {return 0x33;}
else if (fll_freq_hz > 25000000) {return 0x34;}
break;
case 1:
fll_freq_hz = (fll_ref * 1280);
if (fll_freq_hz < 40000000) {return 0x35;}
else if (fll_freq_hz > 50000000) {return 0x36;}
break;
case 2:
fll_freq_hz = (fll_ref * 1920);
if (fll_freq_hz < 60000000) {return 0x37;}
else if (fll_freq_hz > 75000000) {return 0x38;}
break;
case 3:
fll_freq_hz = (fll_ref * 2560);
if (fll_freq_hz < 80000000) {return 0x39;}
else if (fll_freq_hz > 100000000) {return 0x3A;}
break;
}
}
return fll_freq_hz;
} // fll_freq
int fee_fei(int slow_irc_freq)
{
short i;
int mcg_out;
// Check MCG is in FEE mode
if (!((((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) == 0x0) && // check CLKS mux has selcted FLL
(!(MCG_S & MCG_S_IREFST_MASK)) && // check FLL ref is external ref clk
(!(MCG_S & MCG_S_PLLST_MASK)))) // check PLLS mux has selected FLL
{
return 0x2; // return error code
}
// Check IRC frequency is within spec.
if ((slow_irc_freq < 31250) || (slow_irc_freq > 39063))
{
return 0x31;
}
// Check resulting FLL frequency
mcg_out = fll_freq(slow_irc_freq);
if (mcg_out < 0x5B) {return mcg_out;} // If error code returned, return the code to calling function
// Ensure clock monitor is disabled before switching to FEI otherwise a loss of clock will trigger
MCG_C6 &= ~MCG_C6_CME0_MASK;
// Change FLL reference clock from external to internal by setting IREFS bit
MCG_C1 |= MCG_C1_IREFS_MASK; // select internal reference
// wait for Reference clock to switch to internal reference
for (i = 0 ; i < 2000 ; i++)
{
if (MCG_S & MCG_S_IREFST_MASK) break; // jump out early if IREFST sets before loop finishes
}
if (!(MCG_S & MCG_S_IREFST_MASK)) return 0x12; // check bit is really set and return with error if not set
// Now in FEI mode
return mcg_out;
} // fee_fei
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