IEEE1588 Synchronized output reference clock with FRDM-K64F

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IEEE1588 Synchronized output reference clock with FRDM-K64F

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lpham
Contributor I

Hello Everyone,

I need a synchronized reference clock up to 1MHz output from Kinetis K64 for my design, so my thinking is to use 1588 timer ENET_TCCR to create that clock and output to a GPIO.  To do that, it looks like I have to set the Timer Period Register ENET_ATPER to the 1/2 output clock period so my TCCR with output mode 0101 (Toggle Ouput on compare).  Here is what I tested on FRDM-K64F with output 1MHz reference clock at PTC16:

PORT_HAL_SetMuxMode(PORTC,16u,kPortMuxAlt4);     // set timer output

ENET_BWR_ATCR_RESTART(ENET, 0x201);     // set slave mode and start timer.

ENET_WR_ATPER(ENET, 500);                           // set timer period 500nsec

ENET_WR_ATINC(ENET, 20);                              // inc at 50MHz (with Ethernet RMII mode)

ENET_WR_TCCR(ENET, 0, 250);                         // compare toggle at 250nsec

ENET_WR_TCSR(ENET, 0, (5<<2));                    // set compare toggle output

My concerns are:

1. Is this the only way and/or correct way to create a output IEEE1588 synchronized reference clock?

2. Will PTP stack work properly with this fast ATPER period?  If not, what's the shortest period recommended?

3. Look like other 1588 timers with compare capture mode (triggered by external gpio) will be limited to ATPER period of 500nsec captured time which is not really useful!  Is there any other way to capture more realistic timer value, say in seconds.msec.usec.nsec using trigger from external event (GPIO)?

I'm a first timer to IEEE1588, and I appreciate to all feedback and help.

Thank you very much.

Loc

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lpham
Contributor I

After reviewed and ran some tests with PTP, I found it is not possible to create this high frequency based on the synchronized system clock without issue.  While in operation, the PTP clock correction can be from tens of nanosecond to several microseconds depending on the nature of network connection, and that would overflow the TCCR value.  The alternative for me is to look into the synchronized 1PPS pulse output from IEEE1588 module to timestamp all timing activities.  Hope that helps for those having the same need as mine.

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