Frdm k64f prolonged output from pwm after disabling the timer input.

[Navkumar]

Hi, 

I'm working on Frdm k64f kit. I've recently inherited a code base, which has hardware triggered ftm0 pwm, in turn driving two other pwms ftm1 and 2. However when the ftm0 timer is disabled there is a bit of residual data, value high for certain period from one of the pwm's. I have checked the settings and everything looks OK , being fairly new to this processor any help or nudge in the right direction is  much appreciated. Thanks. 

[Robin_Shen]

Hi Navkumar,

Is there any documentation for the code base you got? Can you elaborate on how ftm0 is driving two other pwms ftm1 and 2? Otherwise, it is difficult to understand which phenomenon is correct, corresponding to the fact that you disable the ftm0 timer.

Maybe you can check the configuration of "40.4.10 Registers updated from write buffers" and "40.4.11 PWM synchronization" and "40.4.28 Global time base (GTB)" in K64P144M120SF5RM.

Best Regards,
Robin