Flex bus initialization in K60 for CS[0:5].

[sudheera]

Hi,

I am working on K60 evalution board, in flex bus configuration am able to cofigure fb_cs0 with range from 0x6000_0000 to 0x6FFF_FFFF;

But in same way trying to configure for fb_cs1 to fb_cs5 range start from 0x7000_0000 to 0x7FFF_FFFF (fb_cs1) it's not configured with

followin configuration

  SIM_SCGC7 |= SIM_SCGC7_FLEXBUS_MASK;

  //Set Base address

  FB_CSAR1 = 0x70000000;

  FB_CSCR1  =   FB_CSCR_PS(2)      // 16-bit port

              | FB_CSCR_AA_MASK    // auto-acknowledge

              | FB_CSCR_ASET(0x1)  // assert chip select on second clock edge after address is asserted

              | FB_CSCR_WS(0x1)    // 1 wait state - may need a wait state depending on the bus speed

              ;

  FB_CSMR1  =   FB_CSMR_BAM(0x1FF)  //Set base address mask for 512K address space

              | FB_CSMR_V_MASK    //Enable cs signal

              ;

   //enable BE signals - note, not used in this example

  FB_CSPMCR = 0x12200000;

  //fb clock divider 3

  SIM_CLKDIV1 |= SIM_CLKDIV1_OUTDIV3(0x3);

  // Set the GPIO ports clocks

    SIM_SCGC5 = SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK |

    SIM_SCGC5_PORTD_MASK | SIM_SCGC5_PORTE_MASK;

Tell me if any other configurations required.

[Kan_Li]

Hi,

Seems you didn't initialize the bit of CSMR0[V] , please do it as well . You may refer to the following snapshots for more details about it.

You may also refer to the following example code for help.

Example code:

/* Code Snippet */

int MRAM_START_ADDRESS = 0x60000000;

uint8 wdata8 = 0x00;

uint8 rdata8 = 0x00;

uint16 wdata16 = 0x00;

uint16 rdata16 = 0x00;

uint32 wdata32 = 0x00;

uint32 rdata32 = 0x00;

/* Set Base address */

FB_CSAR0 = MRAM_START_ADDRESS ;

/* Enable CS signal */

FB_CSMR0 |= FB_CSMR_V_MASK;

FB_CSCR0 |= FB_CSCR_BLS_MASK // right justified mode

| FB_CSCR_PS(1) // 8-bit port

| FB_CSCR_AA_MASK // auto-acknowledge

| FB_CSCR_ASET(0x1) // assert chip select on second clock edge after address

is asserted

// | FB_CSCR_WS(0x1) // 1 wait state - may need a wait state depending on the

bus speed

;

/* Set base address mask for 512K address space */

FB_CSMR0 |= FB_CSMR_BAM(0x7);

/* Set BE0/1 to MRAM */

FB_CSPMCR |= 0x02200000;

/* Reference clock divided by 3 */

SIM_CLKDIV1 &= ~SIM_CLKDIV1_OUTDIV3(0xF);

SIM_CLKDIV1 |= SIM_CLKDIV1_OUTDIV3(0x3);

/* Configure the pins needed to FlexBus Function (Alt 5) */

/* this example uses low drive strength settings */

//address/Data

PORTA_PCR7=PORT_PCR_MUX(5); //fb_ad[18]

PORTA_PCR8=PORT_PCR_MUX(5); //fb_ad[17]

PORTA_PCR9=PORT_PCR_MUX(5); //fb_ad[16]

PORTA_PCR10=PORT_PCR_MUX(5); //fb_ad[15]

PORTA_PCR24=PORT_PCR_MUX(5); //fb_ad[14]

PORTA_PCR25=PORT_PCR_MUX(5); //fb_ad[13]

PORTA_PCR26=PORT_PCR_MUX(5); //fb_ad[12]

PORTA_PCR27=PORT_PCR_MUX(5); //fb_ad[11]

PORTA_PCR28=PORT_PCR_MUX(5); //fb_ad[10]

PORTD_PCR10=PORT_PCR_MUX(5); //fb_ad[9]

PORTD_PCR11=PORT_PCR_MUX(5); //fb_ad[8]

PORTD_PCR12=PORT_PCR_MUX(5); //fb_ad[7]

PORTD_PCR13=PORT_PCR_MUX(5); //fb_ad[6]

PORTD_PCR14=PORT_PCR_MUX(5); //fb_ad[5]

PORTE_PCR8=PORT_PCR_MUX(5); //fb_ad[4]

PORTE_PCR9=PORT_PCR_MUX(5); //fb_ad[3]

PORTE_PCR10=PORT_PCR_MUX(5); //fb_ad[2]

PORTE_PCR11=PORT_PCR_MUX(5); //fb_ad[1]

PORTE_PCR12=PORT_PCR_MUX(5); //fb_ad[0]

//control signals

PORTA_PCR11=PORT_PCR_MUX(5); //fb_oe_b

PORTD_PCR15=PORT_PCR_MUX(5); //fb_rw_b

PORTE_PCR7=PORT_PCR_MUX(5); //fb_cs0_b

PORTE_PCR6=PORT_PCR_MUX(5); //fb_ale

/* 8 bit write */

*(vuint8*)(MRAM_START_ADDRESS + n) = 0xAC; // n=offset

/* 8 bit read */

rdata8=(*(vuint8*)(&MRAM_START_ADDRESS + n)); // n = offset

/* 16 bit write */

*(vuint16*)(MRAM_START_ADDRESS + n) = 0x1234; // n=offset

/* 16 bit read */

rdata16=(*(vuint16*)(&MRAM_START_ADDRESS + n)); // n = offset

/* 32 bit write */

*(vuint32*)(MRAM_START_ADDRESS + n) = 0x87654321; // n = offset

/* 32 bit read */

rdata32=(*(vuint32*)(&MRAM_START_ADDRESS + n)); // n = offset

Hope that helps,

B.R

Kan

[sudheera]

Hi Kan Li,

I have set the  FB_CSMR0[v] bit before chip select, this code works fine for CS0. I am not able to set the CS1 to CS5 from start address 0x70000000 to 0x7FFFFFFF.

//#include "common.h"

void TWRK60_flexbus_init(void);

#define MRAM_START_ADDRESS (*(vuint8*)(0x70000000))

/********************************************************************/

void main (void)

{

    uint8 wdata8 = 0x00;

    uint8 rdata8 = 0x00;

    uint16 wdata16 = 0x00;

    uint16 rdata16 = 0x00;

    uint32 wdata32 = 0x00;

    uint32 rdata32 = 0x00;

    uint32 n = 0;

   // printf("\n****MRAM Test****\n");

  //  printf("\nInitializing the FlexBus\n");

    //MCG_FEI_BLPE();

    TWRK60_flexbus_init();

    /*print FlexBus configuration register contents

    printf("FB_CSCR0 is %08x \n\r",FB_CSCR0);

    printf("FB_CSMR0 is %08x \n\r",FB_CSMR0);

    printf("FB_CSAR0 is %08x \n\r",FB_CSAR0);

    printf("FB_CSPMCR is %08x \n\r",FB_CSPMCR);

    printf("SIM_CLKDIV1 is %08x \n\r",SIM_CLKDIV1);

  printf("\nTesting 16-bit write/reads\n");*/

    wdata16=0x1203;   //data to write to mram

  //for(n=0x00010;n<0x001F;n+=2)  //address offset

    while(1)

  {

    n=0x00000;

  *(vuint16*)(&MRAM_START_ADDRESS + n) = wdata16;  //write

  rdata16=0x00;  //clear data variable;

  rdata16=(*(vuint16*)(&MRAM_START_ADDRESS + n));  //read

  //printf("ADDR: 0x%08x WRITE: 0x%04x READ: 0x%04x\n",&MRAM_START_ADDRESS + n,wdata16,rdata16);

  }

}

/********************************************************************/

void TWRK60_flexbus_init(void)

{

/* Enable the FlexBus                                               */

/* Configure the FlexBus Registers for 8-bit port size              */

/*  with separate address and data using chip select 0              */

/* These configurations are specific to communicating with          */

/*  the MRAM used in this example                                   */

/* For K60 tower module - do not set byte lane shift so that data   */

/*  comes out on AD[31:24]                                          */

  SIM_SCGC7 |= SIM_SCGC7_FLEXBUS_MASK;

  FB_CSMR1  =   FB_CSMR_BAM(0x1FF)  //Set base address mask for 512K address space

  | FB_CSMR_V_MASK    //Enable cs signal

  ;

  //Set Base address

  FB_CSAR1 = (uint32)&MRAM_START_ADDRESS;

  FB_CSCR1  =   FB_CSCR_PS(2)      // 16-bit port

   | FB_CSCR_AA_MASK    // auto-acknowledge

   | FB_CSCR_ASET(0x1)  // assert chip select on second clock edge after address is asserted

   | FB_CSCR_WS(0x1)    // 1 wait state - may need a wait state depending on the bus speed

   ;

  //enable BE signals - note, not used in this example

  FB_CSPMCR = 0x12200000;

  //fb clock divider 3

  SIM_CLKDIV1 |= SIM_CLKDIV1_OUTDIV3(0x3);

  // Set the GPIO ports clocks

  SIM_SCGC5 = SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK |

  SIM_SCGC5_PORTD_MASK | SIM_SCGC5_PORTE_MASK;

  /* Configure the pins needed to FlexBus Function (Alt 5) */

  /* this example uses low drive strength settings         */

  PORTB_PCR20 = PORT_PCR_MUX(5);  //  fb_ad[31] used as d[15]

    PORTB_PCR21 = PORT_PCR_MUX(5);  //  fb_ad[30] used as d[14]

    PORTB_PCR22 = PORT_PCR_MUX(5);  //  fb_ad[29] used as d[13]

    PORTB_PCR23 = PORT_PCR_MUX(5);  //  fb_ad[28] used as d[12]

    PORTC_PCR12 = PORT_PCR_MUX(5);  //  fb_ad[27] used as d[11]

    PORTC_PCR13 = PORT_PCR_MUX(5);  //  fb_ad[26] used as d[10]

    PORTC_PCR14 = PORT_PCR_MUX(5);  //  fb_ad[25] used as d[9]

    PORTC_PCR15 = PORT_PCR_MUX(5);  //  fb_ad[24] used as d[8]

    PORTB_PCR6  = PORT_PCR_MUX(5);  //  fb_ad[23] used as d[7]

    PORTB_PCR7  = PORT_PCR_MUX(5);  //  fb_ad[22] used as d[6]

    PORTB_PCR8  = PORT_PCR_MUX(5);  //  fb_ad[21] used as d[5]

    PORTB_PCR9  = PORT_PCR_MUX(5);  //  fb_ad[20] used as d[4]

    PORTB_PCR10 = PORT_PCR_MUX(5);  //  fb_ad[19] used as d[3]

    PORTB_PCR11 = PORT_PCR_MUX(5);  //  fb_ad[18] used as d[2]

    PORTB_PCR16 = PORT_PCR_MUX(5);  //  fb_ad[17] used as d[1]

    PORTB_PCR17 = PORT_PCR_MUX(5);  //  fb_ad[16] used as d[0]

    PORTB_PCR18 = PORT_PCR_MUX(5);  //  fb_ad[15]

    PORTC_PCR0  = PORT_PCR_MUX(5);  //  fb_ad[14]

    PORTC_PCR1  = PORT_PCR_MUX(5);  //  fb_ad[13]

    PORTC_PCR2  = PORT_PCR_MUX(5);  //  fb_ad[12]

    PORTC_PCR4  = PORT_PCR_MUX(5);  //  fb_ad[11]

    PORTC_PCR5  = PORT_PCR_MUX(5);  //  fb_ad[10]

    PORTC_PCR6  = PORT_PCR_MUX(5);  //  fb_ad[9]

    PORTC_PCR7  = PORT_PCR_MUX(5);  //  fb_ad[8]

    PORTC_PCR8  = PORT_PCR_MUX(5);  //  fb_ad[7]

    PORTC_PCR9  = PORT_PCR_MUX(5);  //  fb_ad[6]

    PORTC_PCR10 = PORT_PCR_MUX(5);  //  fb_ad[5]

    PORTD_PCR2  = PORT_PCR_MUX(5);  //  fb_ad[4]

    PORTD_PCR3  = PORT_PCR_MUX(5);  //  fb_ad[3]

    PORTD_PCR4  = PORT_PCR_MUX(5);  //  fb_ad[2]

    PORTD_PCR5  = PORT_PCR_MUX(5);  //  fb_ad[1]

    PORTD_PCR6  = PORT_PCR_MUX(5);  //  fb_ad[0]

    PORTD_PCR8  = PORT_PCR_MUX(6);  //  fb_a

    PORTD_PCR9  = PORT_PCR_MUX(6);  //  fb_a

    PORTD_PCR10  = PORT_PCR_MUX(6);  //  fb_a

    PORTD_PCR11  = PORT_PCR_MUX(6);  //  fb_a

    PORTD_PCR12  = PORT_PCR_MUX(6);  //  fb_a

    PORTD_PCR13  = PORT_PCR_MUX(6);  //  fb_a

    PORTD_PCR14  = PORT_PCR_MUX(6);  //  fb_a

    PORTD_PCR15  = PORT_PCR_MUX(6);  //  fb_a

    PORTA_PCR24  = PORT_PCR_MUX(6);  //  fb_a

    PORTA_PCR25  = PORT_PCR_MUX(6);  //  fb_a

    PORTA_PCR26  = PORT_PCR_MUX(6);  //  fb_a

    PORTA_PCR27  = PORT_PCR_MUX(6);  //  fb_a

    PORTA_PCR28  = PORT_PCR_MUX(6);  //  fb_a

    PORTA_PCR29  = PORT_PCR_MUX(6);  //  fb_a

  //control signals

  PORTB_PCR19 = PORT_PCR_MUX(5);          // fb_oe_b

  PORTC_PCR11 = PORT_PCR_MUX(5);          // fb_rw_b 

  //PORTD_PCR1  = PORT_PCR_MUX(5);          // fb_cs0_b

  PORTD_PCR0  = PORT_PCR_MUX(5);// fb_cs1

  PORTD_PCR0  = PORT_PCR_MUX(5);          // fb_ale

}

Tell me where am doing mistake.

Regards,

Sudheer A

[Kan_Li · Accepted solution]

Hi Sudheer A,

I think maybe there is some misunderstanding between us, what I mean is FB_CSMR0[v] bit should be set even you have initialized FB_CSMR1[V] bit. so TWRK60_flexbus_init() for CS1 should be looked like the following:

void TWRK60_flexbus_init(void)

{

/* Enable the FlexBus                                               */

/* Configure the FlexBus Registers for 8-bit port size              */

/*  with separate address and data using chip select 0              */

/* These configurations are specific to communicating with          */

/*  the MRAM used in this example                                   */

/* For K60 tower module - do not set byte lane shift so that data   */

/*  comes out on AD[31:24]                                          */

  SIM_SCGC7 |= SIM_SCGC7_FLEXBUS_MASK;\

/* Enable CS signal */

  FB_CSMR0 |= FB_CSMR_V_MASK;

  FB_CSMR1  =   FB_CSMR_BAM(0x1FF)  //Set base address mask for 512K address space

  | FB_CSMR_V_MASK    //Enable cs signal

  ;

  //Set Base address

  FB_CSAR1 = (uint32)&MRAM_START_ADDRESS;

  FB_CSCR1  =   FB_CSCR_PS(2)      // 16-bit port

   | FB_CSCR_AA_MASK    // auto-acknowledge

   | FB_CSCR_ASET(0x1)  // assert chip select on second clock edge after address is asserted

   | FB_CSCR_WS(0x1)    // 1 wait state - may need a wait state depending on the bus speed

   ;

.......

}

Hope that helps,

B.R

Kan

[sudheera]

Hi Kan Li,

Thanks for your support, now it's working fine.

Regards,

Sudheer A.