Communication risk of II2C in S9KEAZ128

[jimmyli]

Hi,

      Our customer used S9KEAZ128 to develop producitons before, now one of their productions using I2C in slave mode has been found a risk that showed below.

      Risk: After some repeat start signals, we find the falling edge of SDA signal is near to the rising edge of SCL signal, which will lead to failed commnnication risk.

      I can't find any helpful message in S9KEAZ128 RM.

      Can you help to check and give some tips ?

      Thanks very much.

[RaRo]

Hello @jimmyli,

Can you help to check and give some tips ?

You could try doing a slower transfer or using I2C clock stretching which is a method for I2C devices to slow down or halt the bus by holding the clock line low, this could happen when the slave device needs more time to process the data.

You may find some information about Clock stretching in KEA128 Sub-Family Reference Manual. Section 31.4.1.9. Clock Stretching and Section 31.3.6. I2C Control Register 2 (I2Cx_C2). The SBRC bit will control how clock stretching is implemented.

Best regards, Raul.

[ZhangPei]

Hi Raul,

Thanks for you suggestion!

But I tried to change the register, and it didn't work.

Can you provide some reference initialization code?

[RaRo]

Hello @ZhangPei,

Unfortunately, there is not an example about clock stretching for the KEAZ128. You could use the FRDM_KEA128_I2C examples as a guide to your implementation.

In case you are using a Kinetis device as master to connect with an I2C device, the clock stretching should be done by the slave device. In this case, the slave device should hold the clock signal low until it has data available. There isn't anything that needs to be done to enable clock stretching on the master side.

Best regards, Raul.

[jimmyli]

Hi Raul,

      Thanks for your replying.

      We will try and give a feedback soon.