SDRAM configuration help

[ynaught]

Does anyone have a reference that describes in general how to configure the SDRAM controller in MCF5270 or the like?

All my experience to this point was with SRAM, imagine my surprise when I spent a DAY writing the SDRAM configuration, and an HOUR on the UART.

But anyway, now I've discovered that I've got it wrong somehow.  It works fine but using movem to READ the SDRAM fails in strange ways, I assume having to do with the speed at which that instruction fetches information from the RAM. 

Ideally, I'd like to find a document that discusses the configuration in general terms.  But if someone can give me a hint, that'd be cool too (tho I hope to have it solved by then

I have two Micron MT48LC4M16A2P-75:G chips to make a 32-bit memory, 16MB.  I can read and write individual addresses with this config but only get into trouble with movem (and, I suspect I'll be in trouble when I enable the cache..?)

My initialization function follows:

#define REFRESH_FREQUENCY 64000
#define BUSCLKS_PER_REFRESH (SYSTEM_CLOCK/REFRESH_FREQUENCY)     
#define REFRESH_COUNT (( BUSCLKS_PER_REFRESH / 16) - 1)
#if (REFRESH_COUNT > 0x1ff)
 #error "Refresh Count value calculated is out of bounds."
#endif
 MCF_SDRAMC_DCR   =
                    MCF_SDRAMC_DCR_RC(REFRESH_COUNT) +
                    MCF_SDRAMC_DCR_RTIM(1)        + // 6 clocks (65ns = 5.75 bus clocks)
//                     MCF_SDRAMC_DCR_IS             + Self Refresh is for low-power (sleep) mode
//                     MCF_SDRAMC_DCR_COC            + CKE = Clock enable (normal)
//                     MCF_SDRAMC_DCR_NAM            + We want controller to mux
                    0;
                    
 MCF_SDRAMC_DACR0 =
//                     MCF_SDRAMC_DACRn_IP              + Initiate Precharge All (later)
                    MCF_SDRAMC_DACRn_PS(0)           + // 32-bit port size
//                     MCF_SDRAMC_DACRn_MRS             +
                    MCF_SDRAMC_DACRn_CBM(4)          + // Based on BA0, 1 tied to A22, 23  p.18-8
                    MCF_SDRAMC_DACRn_CASL(2)         + // *** Not positive I've got this right
//                     MCF_SDRAMC_DACRn_RE              +
                    MCF_SDRAMC_DACRn_BA((long)SDRAM)  +
                    0;
 MCF_SDRAMC_DMR0 =
//                     MCF_SDRAMC_DMRn_WP            +
                    MCF_SDRAMC_DMRn_BAM_16M       + // 16MB of RAM
                    MCF_SDRAMC_DMRn_V             +
                    0;

 /*
 Init sequence for SDRAM (p. 18-19):
  1. Wait 100us with SDRAM lines idle.  Maybe this was done.
   2. Configure DCR, DACR, DMR (done, above.)
   3. Issue PALL command, read SDRAM Location, wait Trp. */
 MCF_SDRAMC_DACR0 |= MCF_SDRAMC_DACRn_IP;
 *((long *)SDRAM) = 0;  // Longword Write to first bit of SDRAM
 __asm( "nop");
 __asm( "nop");
//  4. Enable refresh (DACR[RE]) and wait for at least 8 refreshes to occur
 MCF_SDRAMC_DACR0 |= MCF_SDRAMC_DACRn_RE;
 Wait( 64 * 9);
//  5. Check DMR mask bits to make sure you can issue MRS command; change if necessary
   // Big RAM, looks OK
//  6. Issue MRS command: Set DACR[IMRS] then access location in SDRAM (address is the command)
/*  Micron SDRAM command binary: 00 0 00 010 0 000  
                                 | |  |   | |   +-Burst length = 1
                                 | |  |   | +-----Burst type sequential
                                 | |  |   +-------CAS latency = 2 (3 also supported)
                                 | |  +-----------Standard Operation
                                 | +--------------Programmed Burst Length
                                 +----------------Reserved
   That's all 0's except for A5.  RAM A5 connects to CPU A10 (schematic),
   so access SDRAM + 0x400 to send this command.
   *** This command may NOT be valid for the other sources for SDRAM.
 */
 MCF_SDRAMC_DACR0 |= MCF_SDRAMC_DACRn_IMRS;
 *((long *)(SDRAM + 0x400)) = ~0;  // should hit both of them
    

At the end of configuration, the registers contain:

DCR0A = 0x0253

DACR0A = 0x1000A400

DMR0A = 0x00FC0001

[ynaught · Accepted solution]

All hail Melissa the Great (from Motorola Technical Support)!

After some head-scratching, she pointed out that in my configuration of DACR0,   MCF_SDRAMC_DACRn_CASL(2) sets the SDRAM controller for a CAS Latency of 3!!!  Couple that with my configuring the SDRAM for CAS2, and (go figure) I've got problems.

I changed that line to  MCF_SDRAMC_DACRn_CASL(1) and now my RAM test passes flawlessly.  I think I'm ready to enable the cache now.

Thanks again, Melissa!

[ttrans]

I'm having a similar problem on a 5485 processer using a single MT4LC4M32B2B5-71T

[ynaught]

This may be of use to someone who knows much about SDRAM:

dr

D0 = 00000034 D1 = 00000002 D2 = 00000004 D3 = 01000000

D4 = 01000000 D5 = 00000004 D6 = 01000000 D7 = 55AA55AA

A0 = 40000013 A1 = 40100003 A2 = 10000000 A3 = 00012A26

A4 = 0001E294 A5 = F00080D4 A6 = F000FF94 A7 = F000FF3C

PC = 000101C2 SR = 2000 VBR = 00000000 OTHER_A7 = BFB79FFB

CACR = 00000000 ACR0 = 00000000 ACR1 = 00000000

>BKM>di 101c2 10

000101C2 0x4E560000 link.w a6,#$0

000101C6 0x4FEFFFD8 lea $ffd8(sp),sp

000101CA 0x48D73CFC movem.l d2-d7/a2-a5,(sp)

000101CE 0x286E000C movea.l $000c(a6),a4

000101D2 0x2A6E0008 movea.l $0008(a6),a5

000101D6 0x4CD40FFF movem.l (a4),d0-a3

000101DA 0x48D50FFF movem.l d0-a3,(a5)

000101DE 0x4CD50FFF movem.l (a5),d0-a3

000101E2 0x48D40FFF movem.l d0-a3,(a4)

000101E6 0x4CD73CFC movem.l (sp),d2-d7/a2-a5

000101EA 0x4FEF0028 lea $0028(sp),sp

000101EE 0x4E5E unlk a6

000101F0 0x4E75 rts

000101F2 0x4FEFFFF8 lea $fff8(sp),sp

000101F6 0x48D70101 movem.l d0/a0,(sp)

000101FA 0x52B9F0000D98 addq.l #$1,$F0000D98

>BKM>rb

>BKM>ihbc 101d6

>BKM>go

>RUN>

!BREAK! - [msg11001] Internal hardware breakpoint; PC = 0x000101d6 [EVENT Taken]

>BKM>dr

D0 = 00000034 D1 = 00000002 D2 = 00000004 D3 = 01000000

D4 = 01000000 D5 = 00000004 D6 = 01000000 D7 = 55AA55AA

A0 = 40000013 A1 = 40100003 A2 = 10000000 A3 = 00012A26

A4 = F000FF64 A5 = 10000004 A6 = F000FF38 A7 = F000FF10

PC = 000101D6 SR = 2000 VBR = 00000000 OTHER_A7 = BFB79FFB

CACR = 00000000 ACR0 = 00000000 ACR1 = 00000000

>BKM>sidr

!BREAK! - [msg12008] Step instruction; PC = 0x000101DA

D0 = 12345678 D1 = 23456789 D2 = 00000000 D3 = 3456789A

D4 = 456789AB D5 = FFFFFFFF D6 = 56789ABC D7 = 6789ABCD

A0 = 33CC33CC A1 = 789ABCDE A2 = 89ABCDEF A3 = 55AA55AA

A4 = F000FF64 A5 = 10000004 A6 = F000FF38 A7 = F000FF10

PC = 000101DA SR = 2000 VBR = 00000000 OTHER_A7 = BFB79FFB

CACR = 00000000 ACR0 = 00000000 ACR1 = 00000000

>BKM>sidr

!BREAK! - [msg12008] Step instruction; PC = 0x000101DE

D0 = 12345678 D1 = 23456789 D2 = 00000000 D3 = 3456789A

D4 = 456789AB D5 = FFFFFFFF D6 = 56789ABC D7 = 6789ABCD

A0 = 33CC33CC A1 = 789ABCDE A2 = 89ABCDEF A3 = 55AA55AA

A4 = F000FF64 A5 = 10000004 A6 = F000FF38 A7 = F000FF10

PC = 000101DE SR = 2000 VBR = 00000000 OTHER_A7 = BFB79FFB

CACR = 00000000 ACR0 = 00000000 ACR1 = 00000000

>BKM>dml 10000004 12

10000004: 12345678 23456789 00000000 3456789A .4Vx#Eg.....4Vx.

10000014: 456789AB FFFFFFFF 56789ABC 6789ABCD Eg......Vx..g...

10000024: 33CC33CC 789ABCDE 89ABCDEF 55AA55AA 3.3.x.......U.U.

10000034: 000204A4 000204A4 000204A4 33333333 ............3333

10000044: 000204A4 000204A4 ............3333

>BKM>sidr

!BREAK! - [msg12008] Step instruction; PC = 0x000101E2

D0 = 12345678 D1 = 23456789 D2 = 00000000 D3 = 456789AB

D4 = FFFFFFFF D5 = 56789ABC D6 = 56789ABC D7 = 33CC33CC

A0 = 789ABCDE A1 = 89ABCDEF A2 = 89ABCDEF A3 = 55AA55AA

A4 = F000FF64 A5 = 10000004 A6 = F000FF38 A7 = F000FF10

PC = 000101E2 SR = 2000 VBR = 00000000 OTHER_A7 = BFB79FFB

CACR = 00000000 ACR0 = 00000000 ACR1 = 00000000

>BKM>