Those are the power supply sequencing requirements for the MICROPROCESSOR on its own and not the Micro and the "power sequencing IC".
On the eval board, the power supply sequencing requirements are guaranteed by that chip.
If you use some other chip or some other power supply design, you have to ensure that design meets the micro's requirements, and the supplies obey the paragraphs you quoted on power up and down.
All:
The MCF54455 is very forgiving in its power supply needs. The quote at the beginning of this post sounds correct. If the EVDD/SVDD supplies come up first, the pads protect themselves by tristating (high impedance). The ideal scenario is to bring the "I/O" power supplies up first and follow that with the core power supply. The pads have logic in them that waits for the "core logic" IVDD supply in this case to power up before making the pads active. The only really bad thing you can do is find a supply with some very aggressive ramp rate as pointed out in the post. An aggressive ramp rate provides little or no value for you, and instead generates an edge that could falsely trigger the ESD protection circuits and you'd see a very interesting pattern on your oscope where your supply trys to ramp and gets clamped to ground, and then it releases and you'll see your supply try to ramp again...depending on the supply...that is... If you have one of those fancy ones that detects overcurrent, it may just shutdown.
The supplies that we used on the reference board, are just that. ColdFire MPUs do NOT require you to use our supplies and more specifically they are NOT matched. So the supplies are the EVB are just good old fashion switching supplies and provide a good example, but many old fashion LDOs or switchers will work just fine.
Key points to watch out if you choose to not follow the reference design...
Make sure to have a DDR supply that can sink and source current if you use termination resistors. Lots of good cheap regulators for this on the market today.
Make sure you DO NOT tie the VREF and VTT supplies together.
And last...
Try to ramp the "higher voltage" supplies first and have the IVDD supply follow behind. Lots of tricks to doing this. Cascaded linear regulators can do the trick if you are not too concerned about power consumption.
Cheers
JWW
JWW wrote:An aggressive ramp rate provides little or no value for you, and instead generates an edge that could falsely trigger the ESD protection circuits and you'd see a very interesting pattern on your oscope where your supply trys to ramp and gets clamped to ground,Cheers
JWW
Can you provide any more information on what triggers these diodes?
Typing "ESD protection diodes" into Google gets lots of matches for different Freescale products:
http://cache.freescale.com/files/32bit/doc/data_sheet/MPC5200.pdf?fsrch=1&sr=12"The rise times on the power supplies should be slower than 1 microsecond to avoid turning on the internal ESD protectionclamp diodes."Google is better:MCF5373The rise times on the power supplies should be slower than 500 usMCF548xThe rise times on the power supplies should be slower than 1 microsecondMCF54455 Power up sequence - Freescale ForumsThe rise times on the power supplies should be slower than 50 V/millisecondMCF5275Use 1 μs or slower rise time for all supplies. MCF5474The rise times on the power supplies should be slower than 1 microsecond to avoid...
Maybe the different parts do have clamps that are different by a factor of 500, but is it possible that the "500us" ones are a typo and were meant to be "500ns"? 500us is a VERY long time, and needs 1000uF on a linear regulator to get them that slow (at a horribly high current draw).
Very good question.
The pad technology which is where the ESD protection scheme exists are similar across all these product families.
Not the same circuit, but definitely similar methods.
I would do two things.
Submit a service request on the 500us number. I do believe that could be a typo. And the datasheet could be updated as a result.
The MCF5445x family probably has the more accurate spec.
To be honest this really isn't a problem unless you pick something that is generated full swings rail to rail in the NS range.
Again... What you are trying to avoid is a false trigger of the ESD clamps. These clamps are looking for voltage spikes that would damage the part and are clamping the inputs to gnd when the trigger circuits detects a very fast edge on the pwr pins.
-JWW
JWW wrote:
Very good question. ... To be honest this really isn't a problem unless you pick something that is generated full swings rail to rail in the NS range.
Thanks for those comments.
The problem I'm dealing with at the moment is the 30 MILLISECOND power rail ramp time required on the MCF5329 chip we're using to try and stop the SDRAM controller from going ape, locking up the SDRAM chip and stopping the CPU from starting. Plus a bunch of other hardware mods.
I'll provide details when I have a few more answers on this from Freescale.
BTW I tried to properly quote JWW, but the forum pages keep giving errors like:
> An Unexpected Error has occurred.
>
> * Sorry, your request failed. A notification has been sent to the development team for investigation.
> Exception ID: 1291727B