How to read the last part of data from FIFO

[Chethu]

Hi,

I am using MCF52259 controller. For data reception through UART I am using the FIFO FFULL interrupt, the FIFO has 4 registers, if i have to receive 6  bytes i will get 1 interrupt for first 4 bytes and i read them, but the problem is when i receive the last 2 bytes of data i wont get interrupt & lose those 2 bytes.

Please provide solution,how to read <4 bytes of data from 4byte FIFO

Thnx & regards 

Chethu 

[scifi]

You can set up the UART to generate an interrupt on RXRDY condition rather than FIFO FULL. This way you'll get an interrupt for each received character. Or you can poll the UART periodically to detect the remaining 2 bytes.

[Chethu]

Hi Scifi,

Getting interrupt for each byte i thought would be overload for the controller hence i thot of getting the  interrupt only after the FIFO is full. this would reduce the frequency of ISR to 1/4.

If at all i have to go for FIFO how can i get the last two bytes of 6 bytes data(MCF52259 has 4 FIFO receiver registers) 

Thanks & Regards ,

Chethu 

[scifi]

Overload of the controller? I wouldn't worry about that at this stage. How can you know that an interrupt for each byte does overload the MCU and an interrupt for each 4 bytes does not? You can only tell after you have MEASURED that. You shouldn't make life difficult for yourself based on an unfounded concern.

...how can i get the last two bytes of 6 bytes data?

I'm not sure I understand the question. As soon as you read a byte from a full FIFO, the FIFO is ready to receive a new byte.

Say, you've read 4 bytes from the FIFO. You then wait for the other 2 bytes to arrive and you read them from the FIFO. That's it.

[Chethu]

Hi http://forums.freescale.com/t5/user/viewprofilepage/user-id/9363" target="_self,

The 6 bytes here is just an example, the data size may be anything (from 10 bytes to 256 bytes) in such cases how can i know when i have to read the receiver again.

Thanks & Regards,

Chethu

[admin]

Chethu,

> The 6 bytes here is just an example, the data size may be anything (from 10 bytes to 256 bytes) in

> such cases how can i know when i have to read the receiver again.

Usually, message with variable length also includes the header with the message length. Count the remaining bytes after analyzing the header.

[Chethu]

Yevgenit,

I am implementing the modbus protocol and I cant expect the fixed number of data bytes based on the header of the data(I have to handle the error condition also) .

if I receive 7 bytes in place of 6(which the header says) I have to reject the data.

[scifi]

Since you are implementing the MODBUS protocol, having an interrupt for each received byte may be unavoidable. For example, the MODBUS spec says that silent intervals between bytes on the serial line must not exceed 1.5 character times. To detect that, you'll have to set up a timer for each received byte.

[Chethu]

Hi Scifi,

I am not checking for 1.5char time delay between each character as I dont have dat timer resolution(infact i dont wanto keep the task running to check the interval so frequently,my baud rate is 9600 hence 1.5char delay means its 1.25msec). Hence m just checking for 3.5char delay for the end of frame.

[ChrisJohns]

A timer is your only solution unless you interrupt when the FIFO is not empty. Other UARTs I have used have provided inter-character timeout interrupts to handle this case.

Becareful of adjusting the message length to align to the FIFO size. It may work great on a bench but most real world situations have noise and this can add or remove characters from the stream.

[Chethu]

Thnx for the tips chris,

after al i have decided not to go for  FIFO for receiver. But for transmission i could have used the FIFO as the data length is purely in my hand. But the controller MCF52259 has only 2 transmit FIFO registers and there is no FIFO interrupt to subscribe for transmitter.Can u please tell me what the use of transmitter FIFO in this controller when there is no interrupt can be subscribed for it(only for TXREADY the interrupt can be subscribed).

Thanks & Regards ,

Chethu 

[admin]

Chethu,

> Can u please tell me what the use of transmitter FIFO in this controller when there is no interrupt

> can be subscribed for it(only for TXREADY the interrupt can be subscribed).

Usually (I am not familiar with details of MCF52259 UART), UART without Tx FIFO has the shift Tx register and the hold Tx register. When all the bits (except the stop bit) are shifted to the Tx line, content (if the hold register isn't empty) of the hold register is moved to the shift register.

Usually, status bit TXREADY shows empty state of the Tx hold register. Thus, the UART ISR can load the next byte after TXREADY bit (and the related interrupt request) is raised by the UART hardware. Moving the hold register content to the shift register will raise TXREADY bit again.

[aersek]

ColdFire processors have UARTS coupled with DMA. You can use DMA transfer for receive, but there is little problem to measure timeouts in MODBUS protocol. Usage fo DMA for UART transmit is peace of cake, you need to make buffer in RAM which contain output message, start DMA transfer and wait it to finish. In that case you don't have any interrupt exept interrupt on last send character. Search forum for DMA-UART topics.

[Chethu]

Hi aersek,

Thanks a lot for ur help. Now i am planning to implement the transmission part through DMA.I hope that will solve the problem of repeated ISRs for each byte of transmission.

Thanks & Regards,

Chethu 

[admin]

Using single interrupt per received byte is seem the most reliable solutions with satisfactory CPU overhead.

To deal with case of long interrupt latency, the ISR must read FIFO until it is empty.

If you can control format of the received message, extend your message to 8 bytes length with the two dummy bytes. It will permit to use full 4 byte FIFO length and only two interrupts per message.

Another solution: reconfigure UART interrupt logics from full FIFO condition to single byte condition - after receiving first 4 bytes. It reduces quantity of interrupts per message from 6 to 3.