I am having trouble with a stand alone application for ls1021a writing to registers that are not 16-byte aligned in the pcie memory space (memory offset 0x03400000)

[patrickmorrow]

I am having trouble with a stand alone application built in codewarrior for ls1021a writing to registers that are not 16-byte aligned in the pcie memory space (memory offset 0x03400000), is there a setting or something that I am missing?  I am trying to set up ATU values and boundaries and such, and I can read non 16-byte aligned registers (for example 0x0340007C), but when I write modified values back to those registers, the address that gets modified is truncated to the previous 16-byte aligned memory offset (for example 0x03400070).  If I try to modify DRAM offsets (address 0x80000000), there seems to be no issue with writing to addresses that are not 16-byte aligned.

Any insight would be very much appreciated,

Patrick

[addiyi]

Hi Patrik,

How do you try to write pcie memory space? Also, what is the setting for SRDS_PRTCL from your rcw?

Adrian

[patrickmorrow]

Hi Adrian,

Our SRDS_PRTCL value from the RCW (bits 128-135) is 0x10, which should be the values to enable PCIE 1, SATA, and PCIE2.  When trying to write to the memory space we're just doing direct memory manipulations and assignments, the following c snippet is an example of what we're trying do:

#define PCIE_TEST_ADDRESS     0x03400078

*(unsigned int*)(PCIE_TEST_ADDRESS) = 0x12345678;

but instead of address 0x03400078 being manipulated, address 0x03400070 changes

Patrick

[addiyi]

Try to write valid value in 0x03400078. Also you have to write every 16bits, because 0x03400078 it is 16bit register.

Adrian

[patrickmorrow]

Hi Adrian,

We took the default value of 0x2810 that is populated in register 0x03400078 after reset and tried assigning the value 0x4810 (which should just be increasing the max read size) and address 0x03400070 changed while 0x03400078 remained 0x2810.

Patrick

[addiyi]

Here is what I'm done using ccs. This is happened after pcie is configured by uboot (in my case)

Read the values for 0x03400070 and 0x03400078:

(bin) 117 % disp ccs::read_mem 10 0x03400070 4 0 1

                   +0       +4       +8       +C

[0x03400070] 10004200

(bin) 118 % disp ccs::read_mem 10 0x03400078 4 0 1

                   +0       +4       +8       +C

[0x03400078] 10280000

Write new value in 0x03400078

(bin) 119 % ccs::write_mem 10 0x03400078 4 0 0x123f0000

Read again the values for 0x03400070 and 0x03400078:

(bin) 120 % disp ccs::read_mem 10 0x03400078 4 0 1

                   +0       +4       +8       +C

[0x03400078] 12380000

(bin) 121 % disp ccs::read_mem 10 0x03400070 4 0 1

                   +0       +4       +8       +C

[0x03400070] 10004200

As you can see, because 0x03400078 is not 16bit aligned I have to write 32bits. Also, seems that not all bits are writable.

Adrian

[patrickmorrow]

Hi Adrian,

Is it only possible to manipulate the pcie registers through the codewarrior connection server?  We are trying to create a standalone c project through codewarrior and that seems to be giving us a hard time editing the pcie registers.  Is there documentation, or anything, that shows how to initialize the pcie?  Maybe that is where we are getting hung up,

Patrick

[addiyi]

Of course you can manipulate the pcie registers from a c project. My above post just demonstrate that pcie registers are accessible. You have to be careful on how access this register.

You can find helpful info accessing this link: ARM® Developer Suite Developer Guide 6.9.1. Using pointers to access I/O

Adrian

[patrickmorrow]

Hi Adrian,

We've essentially been doing what is suggested in the ARM Developer Suite Guide and that's what's been giving us issues addressing non 16-byte aligned pcie register addresses from our codewarrior standalone application.  When we step through the program, and get to a point where we should be trying to set up the iATU registers, we're still incapable of writing to the ATU_LIMIT, ATU_LOWER_BASE, etc. address offsets. 

We've modified our code to work with the LS1021a TWR development board, and we are getting the same results, in that we cannot modify non 16-byte aligned pcie register addresses.  Is there documentation, or anything, that shows how to initialize the pcie?  Maybe that is where we are getting hung up,

Patrick

[addiyi]

Reference manual should provide information about PCIe initialization. Also, you can take a look in uboot sources, on how uboot initialized PCIe.

Adrian

[patrickmorrow]

Hi Adrian,

We've been trying to emulate the u-boot pcie initialization with no success, we are still unable to modify non 16-byte aligned pcie registers.  Is it something to do with our version of codewarrior?  We are currently using 10.0.0.4 (the last number is a "4", i'm not certain how "0"s there are), but we recently saw that there was an update to version 10.0.0.6 (which has been giving us some different issues).  Is 10.0.0.6 the version you used to verify that codewarrior can communicate with non 16-byte aligned pcie registers via a standalone c project?

Patrick

[addiyi · Accepted solution]

There is no CodeWarrior issue, it is PCIe initialization problem. As you can see in post above, the one uisng ccs command to write in pcie registers, writing registers works fine, but the pcie was initialized by U-Boot. My scenario was to let U-Boot starts and stop it to console, then use ccs to demonstrate the pcie registers access. So, when pcie is correct initialized the pcie registers access works fine, Unfortunately I don't have a CodeWarrior example to initialize pcie. The easy way is to take the pcie initialization sequence from U-Boot.

Adrian