ECC_DETECT ACE error bit enabled after DDR initialization

[Em31]

During the DDR initial enable of the A009803_Erratum process, the ACE bit of the ERR_DECTECT (0xE40) was triggered.

// 3. Set DDR_SDRAM_CFG[MEM_EN]
WRITE32(DDRmc1_SDRAM_CFG_ADDR, (DDRmc1_SDRAM_CFG_VAL | SDRAM_CFG_MEM_EN_MASK));

Can you explain why and what could cause the ACE bit to be triggered?
Also, we are wondering if ACE bit triggering will prevent the QCVS DDR validation process from being completed.

[yipingwang]

the ACE bit can be set when there is an HW issue or when the register setting is not optimized (most cases an incorrect combination of wrlvl_start, clk_adjust, odt, and driver setting can cause the ACE bit to be set).

First we need to make sure the DDR register settings are optimal (with good margins). this can be done using the QCS DDRv tool. Take a good working board and run the DDRv tool to optimize the register setting. then apply the optimized setting to the failing board.