Pulse width Modulator behavior in low and high speed mode

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Pulse width Modulator behavior in low and high speed mode

Contributor I

I am using CW 10.3 with a MC9S08LL64 chip.  I am setting this chip to run in two modes (high 4.2MHz and low 1.05MHz). 

By setting this two modes, I am using a PWM on TPM2CH0 and set it to be 100 Hz period with pulse width of 0, 100 and 200 uSecs.  Generating an interrupt every 10 mSeconds to control the pulse output.

Using Processor expert, creates a HighComp table with 3 values (0x00, 0x01A3 and 0x0347) and a LowComp table with 3 other values (0x00, 0x69 and 0xD2). 

I am finding that while in Low mode and setting the pulse width to 0 uSecs, the pulse is actually having a 100 - 125 uSec width for a long period of time (20 mSec variable).

Everything works correct while in high speed mode.


Any ideas


Jose Alfaro

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Contributor I

An update from previous comment. 

I have narrow it down to the following:

PWM (100Hz period, variable duty cycle and initial polarity set to HIGH).

PWM has events: OnEnd, BeforeNewSpeed and AfterNewSpeed.

Microprocessor having two speeds (high = 4.2 MHz, low = 1.05 MHz).

Every time a change of speed is required (Cpu_SetHighSpeed or Cpu_SetLowSpeed), after adjusting CPU registers, it goes to the PWM code:

void Pulse_SetHigh(void)


  (void)TPM2SC;                        /* Start clearing sequence of TOF bit */

  /* TPM2MOD: BIT15=1,BIT14=0,BIT13=1,BIT12=0,BIT11=0,BIT10=0,BIT9=1,BIT8=1,BIT7=1,BIT6=1,BIT5=0,BIT4=1,BIT3=0,BIT2=1,BIT1=1,BIT0=0 */

  setReg16(TPM2MOD, 0xA3D6U);          

  SetRatio();                          /* Calculate and set up new values of the compare according to the selected speed CPU mode */

  HWEnDi();                            /* Enable/disable device according to status flags */


where it is reseting the clock to the new clock ticks counter, adjusting the Ratio to the new values according to the new clock speed and then... resets the PWM.

Looks like it does not matter if the PWM is enabled or not, there is a time where the output pin is set to the default value (HIGH) and then it is taken to the current value (LOW).

This time when the output is in HIGH and later goes back to LOW does not generate an interrupt. It is happening without control.

Hope this helps to clarify. 

(I created a simple project with CW 10,3 using only the microprocessor and some code to show this behavior)

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NXP Employee
NXP Employee

Hello Jose,

To resume, you're using MCU V10.3 and Processor Expert for MC9S08LL64 chip.

You've problem using the PWM feature.

We've a specific development team for Processor Expert which could be:

      - integrated in CodeWarrior development team,

      - a separate tool which can be used for other dev tool like IAR.

If the feedback provided by Mac will not help you, let me know.

I will contact Processor Expert team and/or Hardware team to get their info.



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Specialist III

Hello Jose,

The extra period between interrupts at the speed transition may be due to the coherency mechanism of the TPM, where changes to the TPM2MOD and the TPM2CH0 registers do not take effect until the next TPM overflow occurs, whereas the change to the bus frequency occurs immediately.

When you are disrupting the normal PWM operation, doing this on TPM overflow interrupt may be inappropriate.  The register settings might better be altered after the occurrence of a CH0 interrupt, when the PWM output state is already low, and should remain so until the next overflow.

However, I can see a different solution that requires no disruption to the normal PWM operation - duty cycle changes do not need to occur within an interrupt.  The proposed alternative is to setup the TPM module for the required period at the low bus frequency, using a prescale division of 1, i.e. TPM2MOD = 10500;

The channel register values for the required duties would be 0, 105, 210.  (I view the use of decimal values to be more meaningful here than hexadecimal.)  You would simply set TPM2SC register for a prescale divisor of 4 when high bus frequency was selected, and a prescale divisor of 1 when low bus frequency was selected.  I would expect that this would not need to be synchronised to any interrupt, since the changes to both parameters would be immediate, and would compensate for each other.



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