MC9S12C32 Memory Allocation

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MC9S12C32 Memory Allocation

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bpaehr
Contributor IV

This is a follow-up question to the question I asked about using an MC9S12C64 in place of an MC9S12C32:

     https://community.nxp.com/message/866581

I was looking into possibly staying with the C32 device.  When I looked at the .MAP file for my most recent project that uses a C32 device, and which I want to build-upon/add-to, I found that there are routines/objects that occupy the memory from 0x4000 to about 0x4315 (see attached .MAP file, in the "OBJECT LIST SORTED BY ADDRESS" section). 

1) What I don't understand is that the C32 device is not supposed to have viable Flash EEPROM for the 0x4000 to 0x7FFF block of addresses.  How is this possible?  Is there some kind of mapping that is done to physically use a PPAGE bank from 0x8000 to 0xBFFF, such that physical address 0x8000 in my C32 device maps to 0x4000 in the memory map?  I've also attached my .PRM file, if that helps to explain where any cross-mapping is occurring, or for any other things that you can point to that describe why this appears to be this way.

2) ***IF*** my memory "usage" is now apparently "spilling over" into the 0x4000 bank (going up to around 0x4315), does that mean I currently have about (0x7FFF - 0x4315) bytes (or 0x3CEA (close to 15K) bytes) still available to me to use for expanded programming without running into any memory-requirement walls?

Thank you in advance for your time.

Bob

Original Attachment has been moved to: P&E_Multilink_CyclonePro_linker.prm.zip
Original Attachment has been moved to: P&E_Multilink_CyclonePro.map.zip

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bpaehr
Contributor IV

Jennie:

Thanks for your response.

Just to be sure that we are on the same page(s), and so that other readers have the same information, I have provided Figure 1-5 from the Device User Guide in reference to "the figure" that you refer to, here:

MC9S12C32 Memory Map.jpg

And, I also include the following in regards to the ROMHM bit in the MISC register:

ROMHM Bit in MISC Reg.jpg

So, from your response, as long as I am operating as a single chip device, and I do nothing with the ROMHM bit which defaults to "0" at RESET, I will have access to, (and the CodeWarrior compiler also knows about), the entire ROM_4000 block of memory from 0x4000 to 0x7FFF, in addition to the normal ROM_C000 block.  CORRECT?

(Figure 1-5 on its own is confusing in that it does not mention that ROMHM must be set to "1" to achieve the map as shown).  If another diagram is available that shows my desired configuration, please include it in your response.

Thank you.:smileyhappy:

Bob

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ZhangJennie
NXP TechSupport
NXP TechSupport

Hello Bob,

Introduction:
Concerning Figure 1-5: The figure shows a useful map, which is not the map out of reset. After reset the map is:
0x0000–0x03FF: Register space
0x0800–0x0FFF: 2K RAM
The flash page 0x003E is visible at 0x4000–0x7FFF in the memory map if ROMHM = 0.
In the figure ROMHM = 1 removing page 0x003E from 0x4000–0x7FFF.

Addressing flash space is:

1) Non banked space $4000~$7FFF - alternative addressing PAGE:WINDOW; where:
- PAGE=n*2; n=0x00~0x1F
- window =0x8000~0xBFFF
2) Non banked $C000~$FFFF - alternative addressing PAGE:WINDOW; where:
- PAGE=n*2-1; n=0x01~0x20
- window =0x8000~0xBFFF

Moreover see Table 1-11. Device Specific Flash PAGE Mapping. On the base of this table the only possibility how to address external memory space is to use not used internal memory space, for example after reset:
- INITRG maps 1k of regs to the 1st 2k block into the memory space 0x0000~0x03FF.
- INITRM maps 2k RAM to the 1st 2k block into the memory space 0x0800~0x0FFF.

- If ROMHM = 0: In this configuration addresses: 0x0400~0x07FF; 0x1000~0x3FFF will access external bus.
- If ROMHM = 1: In this configuration addresses: 0x0400~0x07FF; 0x1000~0x7FFF will access external bus.
  Page 3E is still accessible by means of alternative address PPAGE:WINDOW (PPAGE=n*2; n=0x00~0x1F, WINDOW=0x8000~0xBFFF)

 


Have a great day,
Jennie Zhang

 

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ZhangJennie
NXP TechSupport
NXP TechSupport

Hi Bob,

For 9S12C32, it have two Flash range:

  1. ROM_C000 : from 0xC000 TO 0xFEFF. This range also map to 0x3F8000-0x3FBFFF
  2. ROM_4000: 0x4000 TO 0x7FFF. This range also map to 0x3E8000-0x3EBFFF.

The flash page 0x003E is visible at 0x4000–0x7FFF in the memory map if ROMHM = 0.
In the figure ROMHM = 1 removing page 0x003E from 0x4000–0x7FFF.


Have a great day,
Jennie Zhang

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