Peg:
Thanks for the reply
That's what I thought initially at first was a BR problem. But then I thought why would I receive all my other bytes correctly and ONLY 0x00 fails to 0x80 (with exception of 0xd0 to 0xc7. But I checked the bytes surroudning the 0xd0 and there is no possible way to create a 0xc7 with timing errors)
Either way, I rechecked my BR's and they all appear to be correct
for 9600 Baud on a 20 MHz Bus clock SCIBD = Bus/(16*BR) SCIBD = 9600
SCI1BDL = 0x82
Bus clock is actually 18.87 MHz, Maybe I should make this value closer? I get 0x7A
I am using internal clock
I'm not trimming at all? Not sure what it does or if I even need it?
No framing errors
MPU = (for now) M68DEMO908GB60 Demo board
but will be likely MC9S08GB60 or the GT60 when I'm done debugging
Thanks
**********EDIT************
How does the GB60 board expect SCI packets to be sent? Is it expecting a parity? How many stop bits?
Maybe there is a conflict with what the board expects from SCI and what I'm actually sending. If I only knew what the board wanted...
Message Edited by Tacky on
2007-06-08 02:49 PMMessage Edited by Tacky on
2007-06-08 02:50 PMMessage Edited by Tacky on
2007-06-08 02:52 PMMessage Edited by Tacky on
2007-06-08 02:57 PM