Hello BP,
My understanding is that, when STOP3 mode is exited and SCM is present, the DCO filter registers will have the same value as when STOP3 mode was entered. I suspect this would mean that the time required for the FLL to attain lock will be significantly less than the worst case delay that may be experienced after a POR.
Since your flash clock setting is in the centre of its allowable range, you do have some leeway to allow for SCM temperature drift. However, with 24 hours between wakeups, and the equipment subject to wide temperature variability, it would be more reliable to wait until lock occurs (as for a POR).
On the other hand, if wakeup were to occur much more frequently, say every minute or so, the SCM frequency over this period is far less likely to be affected by ambient temperature variation. If wakeup were to occur at this frequency, wait until FLL lock, and then re-enter stop mode, the flash clock would be likely to remain within range, independent of lock mode.
I would suggest that the overall effect on battery drain, of doing this, would be negligible. The additional non-stop mode operation should amount to considerably less than 3 seconds per day.
If the data being written to flash is critical, I would also suggest that you will need to read back each programmed byte from its flash location, to test for a successful write operation.
Regards,
Mac
Message Edited by bigmac on
2008-04-06 09:50 AM
