IIC i2c example code question - HCS08QRUGSW

[WayneS]

I was looking at the example code in the HCS08QRUGSW.zip file for the GB60 IIC. I was attempting to understand the IIC behavior as slave in receive mode when it receives the stop condition on the bus. For example, I want a master GB60 i2c is sending data to a slave GB60 of an variable length of data. The sequence would be as follows:

Master sends Slave Address followed by data of variable length.
Slave receives address, set up to receive, and stores the data. How does it then detect the Stop condition from the Master?

The code in HCS08QRUGSW.zip in main.c seems to get into the condition of Slave mode, receives data and stores the data in a buffer:

         if (IIC1C_TX == 0) {                /* If data is received store it on the buffer */ 
                I2C_DATA[I2C_COUNTER]=IIC1D;
                I2C_COUNTER++;
                return;
         }

No where can I see how the variable I2C_STEP gets reset back to the ready state.

The main question is how can the IIC unit, as slave in receive mode, determine when the Stop Condition from the Master occurs, that is when the Master terminates transmission?

[mke_et]

This may or may not help. Here are a copy of the notes I made to manually generate I2C with project, which attached a DS1307 to a 9S12 CPU.

;------------------------------------------------------------------DONE
; I2C bus definitions
;
; SC SD
; 1 1 Bus Not Busy leaves it in this condition
; 1 dn Data goes low, start data transer
; 1 up Data goes High, STOP condition
; 1 data Data is valid and static during the HIGH clock state
;
; The HOST (this machine or 'Master') controls the clock. Data is
; bidirectional and can be sent to or from any spot on the wire.
;
; Data is read while clock high, changes occur during clock low
;
; Acknowledge happens after bytes. Host must generate a trailing
; clock for unit to ack. ACK is a 0-bit and a NAK is a 1-bit.
;
; DS1307 address on the I2C bus is 1101000 or 68H
;
; DS1307 only supports 100Khz mode of operation ==== NOTE!!!
;
; Note that the hours register is set up to be 'linear' for 24 hour
; clocks. However, for 12 hour clocks, you have to take the two bits
; for 12/24 and AM/PM into consideration. (In fact, the seconds is
; also linear in operation.)
;
; DS1307 Registers
; 00 - 07 RTC
; 08 - 3F RAM
;
; 00 - Seconds in BCD
; Bit 7 is CH or Clock Halt, set to 0 to run
; 6-4 10's digit of seconds
; 3-0 1's digit of seconds
; 01 - Minutes in BCD
; Bit 7 is 0
; 6-4 10's digit of minutes
; 3-0 1's digit of minutes
; 02 - Hours in BDC
; Bit 7 is 0
; Bit 6 24/12 hour format 0=24
; 5-4 10's digit of hours in 24 hour mode 00-23
; 5 AM/PM bit in 12 hour mode 1=PM
; 4 10's digit of hours in 12 hour mode 1-12
; 3-0 1'd digit of hours
; 03 - Day
; Bit 7-3 are 0
; 2-0 day of week 01-07
; 04 - Date
; Bit 7-6 are 0
; 5-4 10's of day of month 01-31
; 3-0 1's of day of month
; 05 - Month
; Bit 7-5 are 0
; 4 10's of month 1-12
; 3-0 1's of month
; 06 - Year
; Bit 7-4 10's of year 00-99
; 3-0 1's of year
; 07 - Control
; Bit 7 Out Controls OUT if not clock
; 6-5 are 0
; 4 SQWE Enables clock on OUT
; 3-2 are 0
; 1-0 RSx Select for SQWE
;
; To write to the DS1307
; Generate a START
; Send DS1307 7-bit address byte followed by Write bit
; DS1307 should ACK
; Send word address to set register pointer
; DS1307 should ACK
; Send bytes of data
; DS1307 should ack each byte
; Generate a STOP
;
; To read the DS1307
; Generate a START
; Send DS1307 7-bit address byte followed by Read bit
; DS1307 should ACK
; Generate clocks to read data
; Host sends ACK for each byte except last. Send NAK
; Generate a STOP
;
; To set the register address, write to the DS1307 to set the register
; address. The part will ACK. At that point, continue sending if it
; is write data, or do a restart followed by the adress and reads.
;
; A 3-byte write sequence would look like this:
; S-ZZZZZZZ-W-A-LLLLLLLL-A-DDDDDDDD-A-DDDDDDDD-A-DDDDDDDD-A-P
;
; A 3-byte read sequence would look like this:
; S-ZZZZZZZ-R-A-DDDDDDDD-A-DDDDDDDD-A-DDDDDDDD-N-P
;
; S - Start condition
; Z - Device Address bits (total of 7 bits ONLY)
; P - Stop condition
; A - Acknowledge Sent by either end (0-bit)
; N - NOT Acknowledge sent by host to signal no more (1-bit)
; W - write command at the read/write bit (a 0-bit)
; R - read command at the read/writebit (a 1-bit)
; L - Location of register to start at (8 bits)
; D - Data bits (8 bits)
;
; I2C pins are as follows:
; Clock Port J bit 7 Always an output
; Data Port J bit 6 Output and input
;
; These routines make some assumptions to simplify programming.
; Clock pin is ALWAYS an output
;
; In idle, clock and data are left high and both are outputs
;
; When busy, clock is left low, data in indeterminate
;
; Start assumes data and clock are both high. Bus must be output
;
; To go idle, use the STOP routine
;
; When sending data, the host can simply just send a STOP after the
; last byte sent gets an ACK from the chip. However, when reading
; data, the host should respond with a NAK when it wants no more
; data to be sent, followed by the STOP

[kef]

IIC module doesn't have status bits that could be used to detect stop condition in slave mode, or generate interrupt on stop condition.

You wonder when you should reset array index in slave mode. IAAS bit is set on address match. IAAS==1 is good moment to reset pointers and indexes. I wonder why HCS08QRUGSW doesn't use it.

Higher layer protocol could be used to substitute stop detection. You expect say 2 bytes from master. So you expect stop condition after 2nd data byte. If stop detection is absolute must in your case, then you should look towards using keyboard module or wiring SDA and SCL to pins with interrupt capability :smileysad: