Clock Cycles for Branch Instructions

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Clock Cycles for Branch Instructions

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Nevo
Contributor I
I'm porting my mind from the world of PIC chips to HCS08.
 
In the PIC world, a conditional branch instruction takes so many clock cycles to perform, plus a few (2, I think) additional cycles if the branch is taken.
 
I don't see the same documented in the HCS08 instruction set. Does a conditional branch instruction take the same number of cycles whether or not the branch is taken?
 
Thanks,
 
Nevo
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Alban
Senior Contributor II
Hello !
 
I would advise the S08 CPU Reference Manual which details every intruction available and their access.
 
Page 145 will interest you.
 
HCS08RMV1 
HCS08 Family Reference Manual
 
Cheers,
Alban.
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Nevo
Contributor I
Thank you, gentlemen!  (Alban, I was indeed reading that reference.)
 
So in a CodeWarrior disassembly, I see this (I wrote the code in assembler):
 
Code:
829:      CPX m_ChannelDimValue:20;  0096 c30014   [4]             CPX   m_ChannelDimValue:20  830:      BNE testCh21;  0099 2602     [3]             BNE   L9D ;abs = 009d  831:      ORA #16;  009b aa10     [2]             ORA   #16  009d          [5]     L9D:      832:    testCh21:  833:      CPX m_ChannelDimValue:21;  009d c30015   [4]             CPX   m_ChannelDimValue:21  834:      BNE testCh22;  00a0 2602     [3]             BNE   LA4 ;abs = 00a4  835:      ORA #32;  00a2 aa20     [2]             ORA   #32  00a4          [5]     LA4:      836:    testCh22:

 
What is the [5] on the lines with the L9D: and LA4: labels?  I'm trying to figure out what instruction there takes 5 clock cycles.
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Encoder
Contributor I
The disassembled sample is fairly cryptic, I suspect not being correctly formatted with too many line feeds.
 
No istruction in this sample is longer than 4 cycles (CPX opr16a)
L9D  and  L4A are alternate labels for  testCh21:  and  testCh22
 
It seems to me that [5] is the alternate clock counting to reach the label when the branch is not performed and the intermediate instruction (ORA #opr8i) is done.
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Nevo
Contributor I
Thanks, Encoder.
 
It was a good hypothesis.  I tested it by adding NOPs to my code but the pesky [5] by the label remains.
 
I see, however, that there's a separate forum for CodeWarrior issues, so I'm going to drop this thread and start a new thread in the CodeWarrior forum.
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bigmac
Specialist III
Hello Nevo,
 
Yes, three bus cycles whether or not the branch is taken.
 
Regards,
Mac
 
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