230kbaud with ICS? - MC9S08QE128

[hek]

A short question, is it even possible to get 230400 baud rate on the SCI with a bus clock from the ICS? In that case, what IRC and dividers do you guys purpose?

Best regards Henrik

[bigmac]

Hello Henrik,

Using a 32.768 kHz crystal, it is possible to generate a bus frequency of 14.9425 MHz.  This may be used for a baud rate of close to 230400 bits per second, with a divisor value of 4.  The error would be +1.3 percent, which should be sufficiently accurate.

However, this may not be the issue.  When receiving a data stream, the transmission time for each byte will amount to 640 bus cycles.  The ISR processing time must be completed in considerably less cycles, to prevent overrun, and to allow sufficient time for non-interrupt code to execute.  You will also need to consider whether other interrupt sources can cause an SCI overrun, by delaying the receive processing.

Regards,

Mac

[hek]

Thank you Mac för your response!

Actually i maniaged to generate a bus freq of 14.713 MHz (it varries some from time to time, but not more then 0.5% or somehting like that, which i can live with).
Although, im not sure how this is possible. The RM says that the DCO range should be between 16-20MHz in the low range. Might this be very specific for this mcu?

This is the setup code:

Code:

void MCU_Init(void) { SOPT1 = 0x23;          /* Watchdog disable. Stop Mode Enable. Background Pin enable. RESET pin enable */   // ICSTRM = 0xA5;  // Default ICSTRM = 0x0D;   // Configure internal clock ICSSC = 0x01; ICSC1 = 0x04;  ICSC2 = 0x06;   while (ICSC1_CLKS != ICSSC_CLKST) {}  // wait for clk state to match clk select SCGC1 = 0x01;          /* Bus Clock to the SCI1 module is enable */ SCGC2 = 0x00;          /* Disable Bus clock to unused peripherals */}

The uart wont run at 230kbaud all the time, just in the initial phase. After that I will clock it down to 57k6, so hopefully I wont have a overrun problem...

Best regards
Henrik

[bigmac]

Hello Henrik,

Within the Reference Manual document, the last entry of Table 11.7, using a FLL factor of 1824, produces a DCO frequency of 59.77 MHz.  This value divided by four will give the required bus frequency.

Regards,

Mac