PIC problem

[masasi]

Hi,

I am using a P1012 board, I have configured a global timer on PIC as proposed in https://community.freescale.com/thread/357073. I also configure gigabit Ethernet from uboot and I find two possible behaviors on my processor:

- If Ethernet cable is not connected and I configure global timers on the PIC with my init_clock() library function shown below everything works fine.

- If Ethernet cable is connected (sending valid information to microprocessor but the microprocessor is not yet processing those messages) before calling init_clock() library function, once I try to restart the PIC after the global timer configuration, I get the following exception:

NIP: 00000500 XER: 20000000 LR: 00067F14 REGS: 3fa6b748 TRAP: 0700 DAR: 00000000 MSR: 00021200 EE: 0 PR: 0 FP: 0 ME: 1 IR/DR: 00 GPR00: 00067F14 3FA6B838 3FE6BF04 00000000 00000032 00000040 3FFC7E58 00000000 GPR08: 000F65C0 00000020 00000020 3FA6B838 44022084 82C4195D 3FFBB4E8 00000000 GPR16: 3FFF064C 00000000 3FE73348 00497A38 00400000 00000000 00000000 00000001 GPR24: 3FFDD310 3FF78EB4 00000000 3FE7335C 00000000 3FE7335C 3FFC3C18 3FA6B838 ** Illegal Instruction ** Call backtrace: 00067F14 00067A08 3FF78F1C 3FF799D8 3FF79B1C 3FF8433C 3FF89E70 3FF8A4D8 3FF897D8 3FF8E254 3FF77C88 3FF7164C Program Check Exception ### ERROR ### Please RESET the board ###

I believe this is due to the interrupts the etsec and MDIO are sending to the PIC because the Ethernet messages are not being treated yet, is this correct? I have not masked any etsec interruption(IMASK set to 0) and the DISR register is set to 1s in order to avoid sending interrupts to the PIC.TEMASK and PEMASK are also set to 0.

I would like to know how can I disable all kind of interruptions from the etsec so I do not get this exception.

Thanks in advance!

/***************************************************************************************/

void init_clock(void) {   

     ccsr_pic_t *pic = (ccsr_pic_t *)0xFF740000;

     unsigned int *p;   

     unsigned int il,m,n;   

     int *pic_gcr;   

     int *pic_tcr0;   

     int *pic_gtvpr;   

     int *pic_ctpr;   

     int *pic_gtbcr;   

     int *maccfg1;       

     maccfg1=0xff7b1500;   

     /* Disable Transmit and Receive */   

     *maccfg1= ~(0x00000004 | 0x00000001);      

     //Reset PIC   

      *(unsigned int *)&pic->gcr=0x80000000;       

     __asm__("wrteei 0\n");   

     // mask all external interrupts

     p=(unsigned int *)&pic->eivpr0;

     for (il=0; il<12; il++) {

           *p=0x80000000+il; p +=8;

      }

     *(unsigned int *)&pic->ctpr=0x0;

     // the highest priority for processor tasks

     *(unsigned int *)&pic->ctpr0=0x0;   

     // set mixed mode.

     *(unsigned int *)&pic->gcr=0x20000000;

     // Interrupts are handled by the normal priority and delivery mechanisms of the PIC.   

     // clear all spurious interrupts

     m=pic->frr;

     // read number of interrupts

     m >>=16;

     m &=0x7FF;

     for(il=m;il>0;il--) {

           n=pic->iack;

          if (n!=0xFFFF) {

               pic->eoi=0;

           }

     }

     for(il=m;il>0;il--)

     {

          n=pic->iack0;

          if (n!=0xFFFF) {

               pic->eoi0=0;

          }

     }

     //Init Global Timer

     //Configure clock source   

     pic_tcr0=0xFF741300;   

     *pic_tcr0=0x0;   

     //Set priority and vector of GTVPR   

     pic_gtvpr=0xFF741120;   

     *pic_gtvpr=0x000F1A1B;   

     //Set GCR[M] to be mixed mode   

     *pic_gcr|=0x20000000;   

     //Set base counts   

     pic_gtbcr=0xFF741110;   

     *pic_gtbcr=0x8000136E;   

     //Enable counting   

     *pic_gtbcr=0x136E;   

     install_handler (timer_handler);   

      __asm__("wrteei 1\n");

}

[bpe]

Check how you disable eTSEC:

>*maccfg1= ~(0x00000004 | 0x00000001);

Besides that it is recommended to gracefully stop eTSEC before disabling it (See P1021RM, 15.9.3.2),

this actually writes all MACCFG1 bits with all ones, except for Tx_EN and Rx_EN. With this,

you initiate ll types of reset and internal loopback at the same time. Not sure it is what was intended.

Did you mean this:

*maccfg1 &= ~(0x00000004 | 0x00000001);

[bpe]

eTSEC comes out of reset with all interrupts disabled.  u-Boot does not use eTSEC interrupts and does not unmask any.

If you want eTSEC not to send any interrupt to PIC, it is sufficient to leave IMASK and MDIO_IMASKM in their

reset state or write with zeroes if they have been modified. If you wish to disable eTSEC interrupts at the PIC level,

set  M bit in the corresponding IIVPR register. Note that in IMASK one means the corresponding interrupt is unmasked (enabled)

while in xIVPR M==1 means the interrupt is masked.

In general, it is not possible to establish what is wrong with your interrupts without debugging. If you suspect there are

unexpected interrupts, read IACK  to see which PIC interrupt has  caused assertion of int to the core.

To see all active PIC interrupt requests, scan all IVPRs and check A bits.

Have a great day,
Platon

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