Hello *,
we have a IMX53 board, based on LOCO, but we adding the MT29F8G08ABABA NAND using NANDF_D[7:0], CS0, WP_B#.
Booting with kernel it work good, infact I use the NAND as rootfs, I have also write a uImage kernel in a partition in 0x1000000 position, but when I load it in u-boot I obtain:
MR&D NSIP Feb 9 2015 18:48:13> nand read 0x70800000 0x1000000 0x8000
NAND read: device 0 offset 0x1000000, size 0x8000
32768 bytes read: OK
MR&D NSIP Feb 9 2015 18:48:13> md.b 0x70800000 0x10
70800000: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
...
I can't read (I'm sure that in this location there is a Kernel image) obtain only 0xFF for all data.
I can't also write:
MR&D NSIP Feb 9 2015 18:25:49> nand erase 0x0 0x80000
NAND erase: device 0 offset 0x0, size 0x80000
nand0: MTD Erase failure: -5
OK
In the board file, we setup nfc:
#ifdef CONFIG_MXC_NAND
void setup_nfc(void)
{
u32 i, reg;
u32 cfg = (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
PAD_CTL_DRV_HIGH);
#define M4IF_GENP_WEIM_MM_MASK 0x00000001
#define WEIM_GCR2_MUX16_BYP_GRANT_MASK 0x00001000
reg = __raw_readl(M4IF_BASE_ADDR + 0xc);
// reg &= ~M4IF_GENP_WEIM_MM_MASK;
reg |= M4IF_GENP_WEIM_MM_MASK; //NANDF on PATA_DATA
__raw_writel(reg, M4IF_BASE_ADDR + 0xc);
// for (i = 0x4; i < 0x94; i += 0x18) {
// reg = __raw_readl(WEIM_BASE_ADDR + i);
// reg &= ~WEIM_GCR2_MUX16_BYP_GRANT_MASK;
// __raw_writel(reg, WEIM_BASE_ADDR + i);
// }
/* To be compatible with some old NAND flash,
* limit NFC clocks as 34MHZ. The user can modify
* it according to dedicate NAND flash
*/
clk_config(0, 34, NFC_CLK);
mxc_request_iomux(MX53_PIN_NANDF_CS0,
IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_NANDF_CS0, cfg | PAD_CTL_HYS_ENABLE);
// mxc_request_iomux(MX53_PIN_NANDF_CS1,
// IOMUX_CONFIG_ALT0);
// mxc_iomux_set_pad(MX53_PIN_NANDF_CS1,
// PAD_CTL_DRV_HIGH);
// mxc_request_iomux(MX53_PIN_NANDF_CS2,
// IOMUX_CONFIG_ALT0);
// mxc_iomux_set_pad(MX53_PIN_NANDF_CS2,
// PAD_CTL_DRV_HIGH);
// mxc_request_iomux(MX53_PIN_NANDF_CS3,
// IOMUX_CONFIG_ALT0);
// mxc_iomux_set_pad(MX53_PIN_NANDF_CS3,
// PAD_CTL_DRV_HIGH);
mxc_request_iomux(MX53_PIN_NANDF_RB0,
IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_NANDF_RB0, cfg | PAD_CTL_HYS_ENABLE);
mxc_request_iomux(MX53_PIN_NANDF_CLE,
IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_NANDF_CLE, cfg | PAD_CTL_HYS_ENABLE);
mxc_request_iomux(MX53_PIN_NANDF_ALE,
IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_NANDF_ALE, cfg | PAD_CTL_HYS_ENABLE);
//gpio6->9 | WP#0 Write Protect
mxc_request_iomux(MX53_PIN_NANDF_WP_B,
IOMUX_CONFIG_ALT0);
// reg = readl(GPIO6_BASE_ADDR + GPIO_GDIR);
// reg |= 0x200;
// writel(reg, GPIO6_BASE_ADDR + GPIO_GDIR);
//
// reg = readl(GPIO6_BASE_ADDR + GPIO_DR);
// reg |= 0x200;
// writel(reg, GPIO6_BASE_ADDR + GPIO_DR);
mxc_iomux_set_pad(MX53_PIN_NANDF_WP_B, cfg | PAD_CTL_HYS_ENABLE);
mxc_request_iomux(MX53_PIN_NANDF_RE_B,
IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_NANDF_RE_B, cfg | PAD_CTL_HYS_ENABLE);
mxc_request_iomux(MX53_PIN_NANDF_WE_B,
IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_NANDF_WE_B, cfg | PAD_CTL_HYS_ENABLE);
mxc_request_iomux(MX53_PIN_ATA_DATA0,
IOMUX_CONFIG_ALT3);
mxc_iomux_set_pad(MX53_PIN_ATA_DATA0, cfg);
mxc_request_iomux(MX53_PIN_ATA_DATA1,
IOMUX_CONFIG_ALT3);
mxc_iomux_set_pad(MX53_PIN_ATA_DATA1, cfg);
mxc_request_iomux(MX53_PIN_ATA_DATA2,
IOMUX_CONFIG_ALT3);
mxc_iomux_set_pad(MX53_PIN_ATA_DATA2, cfg);
mxc_request_iomux(MX53_PIN_ATA_DATA3,
IOMUX_CONFIG_ALT3);
mxc_iomux_set_pad(MX53_PIN_ATA_DATA3, cfg);
mxc_request_iomux(MX53_PIN_ATA_DATA4,
IOMUX_CONFIG_ALT3);
mxc_iomux_set_pad(MX53_PIN_ATA_DATA4, cfg);
mxc_request_iomux(MX53_PIN_ATA_DATA5,
IOMUX_CONFIG_ALT3);
mxc_iomux_set_pad(MX53_PIN_ATA_DATA5, cfg);
mxc_request_iomux(MX53_PIN_ATA_DATA6,
IOMUX_CONFIG_ALT3);
mxc_iomux_set_pad(MX53_PIN_ATA_DATA6, cfg);
mxc_request_iomux(MX53_PIN_ATA_DATA7,
IOMUX_CONFIG_ALT3);
mxc_iomux_set_pad(MX53_PIN_ATA_DATA7, cfg);
}
#endif
In the Identification file ndand_ids.c we add:
,
{"ONFI NAND 3,3V 8-bit", 0x38, 0, 1024, 0, LP_OPTIONS },
,..
In nand_device_info.c we add
,
{
.end_of_table = false,
.manufacturer_code = 0x2c,
.device_code = 0x38,
.cell_technology = NAND_DEVICE_CELL_TECH_SLC,
.chip_size_in_bytes = 1LL*SZ_1G,
.block_size_in_pages = 128,
.page_total_size_in_bytes = 4*SZ_1K + 224,
.ecc_strength_in_bits = 16,
.ecc_size_in_bytes = 512, //540,
.data_setup_in_ns = 25,
.data_hold_in_ns = 15,
.address_setup_in_ns = 10,
.gpmi_sample_delay_in_ns = 6,
.tREA_in_ns = -1,
.tRLOH_in_ns = -1,
.tRHOH_in_ns = -1,
"MT29F8G08ABABA",
},
{true}
In board file header, we add:
//#define CONFIG_MTD_DEBUG
#define CONFIG_MTD_DEBUG_VERBOSE 1000
#define CONFIG_CMD_MTDPARTS
#define CONFIG_JFFS2_CMDLINE
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define MTDIDS_DEFAULT "nand0=nand0"
//#define MTDPARTS_DEFAULT "mtdparts=nand0:0xc00000@0x0(bootloader),0x400000@0xc00000(factory.id),0x500000@0x1000000(nand.kernel),10000000@0x1500000(nand.rootfs),0x10000000@0x11500000(nand.app),-@0x21500000(nand.rwfs)"
#define MTDPARTS_DEFAULT "mtdparts=nand0:0xc00000@0x0(bootloader),0x400000@0xc00000(factory.id),0x500000@0x1000000(nand.kernel),-@0x1500000(nand.all)\0"
#define MTD_ACTIVE_PART "nand0,1"
/* Enable below configure when supporting nand */
#define PPCHAMELON_NAND_TIMER_HACK
#define CONFIG_CMD_NAND
#define CONFIG_MXC_NAND
#define CONFIG_CMD_NAND_LOCK_UNLOCK
#define CONFIG_SYS_NAND_PAGE_4K
/* NAND FLASH driver setup */
#define CONFIG_SYS_NAND_MAX_CHIPS 8
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_NAND_FW_16BIT 0 /* 1: 16bit 0: 8bit */
#define CONFIG_CMD_NAND_LOCK_UNLOCK
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
| CSOR_NAND_PGS_4K /* Page Size = 4K */ \
| CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
| CSOR_NAND_PB(128)) /*Pages Per Block = 128 */
#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
//#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_FLASH
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x07) | \
FTIM0_NAND_TWH(0x0a))
#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \
FTIM1_NAND_TWBE(0x39) | \
FTIM1_NAND_TRR(0x0e) | \
FTIM1_NAND_TRP(0x18))
#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
FTIM2_NAND_TREH(0x0a) | \
FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3 0x0
Please refer these resources regarding adding new NAND:
1.
https://community.freescale.com/message/295870#295870
2.
Section 7.4.4 (NAND Flash Driver and Commands) of AN4173
http://cache.freescale.com/files/dsp/doc/app_note/AN4173.pdf
Have a great day,
Victor
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Hello,
I re-check the implementation, but I don't understand the problem.
My suspect is that the basic driver need some fix for this nand, I also tried
.page_total_size_in_bytes = 4*SZ_1K + 218,
but the problem remain, seems a fake read and a fake write...
Anyone use this NAND with U-BOOT?