In a 68000 system the E clock (originally the cycle clock for the 6800 CPU) is generated by dividing the system clock by 10 - the E clock was low for six clocks and high for four clocks. At the original 68K speed of 10 MHz this gave a suitable 1 MHz clock for 6800 peripheral devices.
When the VPA signal is activaated in response to a external cycle, the CPU will synchronize to the E clock and terminate the cycle after the next active E clock.
Since your interrupt is not synchronized to the E clock, there is a random delay based on the state of the E clock when the interrupt acknowledge occures.
Regards,
Hugh