Hello,
I am currently working with imx SPI driver on an imx6. I am using a kernel based on the 3.10 branch of linux-fslc.
I am not used to DMA transfer, but what I understand about DMA is that they should let the CPU do others tasks when a transfer through DMA is in progress.
But I have the feeling that when the DMA transfer is initialized and then triggered, the CPU is waiting actively for DMA transfer to finish.
In the following code, I see a call to wait_for_timeout_completion which is a not interruptible function. Can you confirm me that this means that when my CPU perform a SPI transfer it is blocked waiting the end of the DMA transfer ?
| static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx, |
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| struct spi_transfer *transfer) |
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| struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL; |
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| struct spi_master *master = spi_imx->bitbang.master; |
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| struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg; |
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| desc_tx = dmaengine_prep_slave_sg(master->dma_tx, |
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| tx->sgl, tx->nents, DMA_TO_DEVICE, |
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| DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
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| desc_tx->callback = spi_imx_dma_tx_callback; |
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| desc_tx->callback_param = (void *)spi_imx; |
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| dmaengine_submit(desc_tx); |
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| struct scatterlist *sgl_last = &rx->sgl[rx->nents - 1]; |
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| unsigned int orig_length = sgl_last->length; |
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| int wml_mask = ~(spi_imx->rx_wml - 1); |
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| * Adjust the transfer lenth of the last scattlist if there are |
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| * some tail data, use PIO read to get the tail data since DMA |
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| * sometimes miss the last tail interrupt. |
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| left = transfer->len % spi_imx->rx_wml; |
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| sgl_last->length = orig_length & wml_mask; |
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| desc_rx = dmaengine_prep_slave_sg(master->dma_rx, |
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| rx->sgl, rx->nents, DMA_FROM_DEVICE, |
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| DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
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| desc_rx->callback = spi_imx_dma_rx_callback; |
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| desc_rx->callback_param = (void *)spi_imx; |
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| dmaengine_submit(desc_rx); |
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| reinit_completion(&spi_imx->dma_rx_completion); |
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| reinit_completion(&spi_imx->dma_tx_completion); |
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| /* Trigger the cspi module. */ |
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| spi_imx->dma_finished = 0; |
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| spi_imx->devtype_data->trigger(spi_imx); |
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| dma_async_issue_pending(master->dma_tx); |
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| dma_async_issue_pending(master->dma_rx); |
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| /* Wait SDMA to finish the data transfer.*/ |
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| ret = wait_for_completion_timeout(&spi_imx->dma_tx_completion, |
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| IMX_DMA_TIMEOUT(transfer->len)); |
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| pr_warn("%s %s: I/O Error in DMA TX:%x\n", |
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| dev_driver_string(&master->dev), |
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| dev_name(&master->dev), transfer->len); |
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| dmaengine_terminate_all(master->dma_tx); |
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| ret = wait_for_completion_timeout(&spi_imx->dma_rx_completion, |
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| IMX_DMA_TIMEOUT(transfer->len)); |
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| pr_warn("%s %s: I/O Error in DMA RX:%x\n", |
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| dev_driver_string(&master->dev), |
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| dev_name(&master->dev), transfer->len); |
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| spi_imx->devtype_data->reset(spi_imx); |
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| dmaengine_terminate_all(master->dma_rx); |
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| /* read the tail data by PIO */ |
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| void *tmpbuf = transfer->rx_buf + transfer->len - left; |
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| while (readl(spi_imx->base + MX51_ECSPI_STAT) & 0x8) { |
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| readl(spi_imx->base + MXC_CSPIRXDATA); |
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| spi_imx->dma_finished = 1; |
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| spi_imx->devtype_data->trigger(spi_imx); |
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| pr_warn_once("%s %s: DMA not available, falling back to PIO\n", |
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| dev_driver_string(&master->dev), |
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}
