How to control tDQS, tDQ & etc. timing parameters in DDR initialization script ?

[peteramond]

Hi All,

Dear Alien

This is a custom hardware design with;

Processor - iMAX6Q - MCIMX6Q6AVT10AC

RAM - 933MHz Micron DDR3L - MT41K256M16TW-107 IT:P

1) Here is the configuration for the script. Can you check and tell me the configurations are correct or not ?

2) Don't you have different script generator for DDR3L type memories (Low Power RAM) ? 

3) In memory type I don't have to select DDR3L-933 option. What should I select ?

4) In DRAM clock frequency I don't have to select any option for 933MHz. What should I select ?

5) Under SI configuration section what should I select for 

DRAM DSE Setting - DQ/DQM (ohm)

DRAM DSE Setting - ADDR/CMD/CTL (ohm)

....etc.

6)  If I couldn't control impedance of single ended and DATA signals of DDR layout any method to control timing in while calibration process?

Can you give me an idea on this SI configuration parameters. Under which conditions of the memory should we change those values and how ?

Waiting for a detailed explanation for this. 

Regards & Thanks,

Peter.

[Yuri]

Hello,

 Use the following

Freescale i.MX6 DRAM Port Application Guide-DDR3 

In particular, it contains section 2.1.3 [SI (Signal Integrity) Consideration].

As for memory tools:

i.MX6DQ SABRE SDP/B DDR3 Register Programming Aid 

To check memory settings:

https://community.nxp.com/docs/DOC-105652 

  i.MX6 MMDC supports maximal DRAM clock frequency of 532 MHz, therefore

it makes sense to apply DDR3-1066 (most “relaxed” ) timing specs for memory

parameters: tRCD = 15ns, tRC=52.5ns, tRAS=37.5ns.

 
Have a great day,
Yuri

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------